Modeling and Simulation of Tunneling Current Density for Ultra Thin MOS Devices

2016 ◽  
Vol 860 ◽  
pp. 30-34 ◽  
Author(s):  
Niladri Pratap Maity ◽  
Reshmi Maity ◽  
R.K. Thapa ◽  
S. Baishya
Keyword(s):  
Current Density ◽  
Current Flow ◽  
Tunneling Current ◽  
Oxide Thickness ◽  
Oxide Semiconductor ◽  
Tunneling Model ◽  
Mos Devices ◽  
Theoretical Predictions ◽  
Numerical Device ◽  
Mos Gate

In this paper, an analytical model for evaluation of tunneling current density of ultra-thin Metal Oxide Semiconductor (MOS) devices is presented. Results have been obtained for a wide variation of oxide thickness and biasing condition having doping concentration of 1 x 1017 cm-3. The investigation for the tunneling current density is limited to low temperatures, so that any thermal involvement to current flow can be neglected. The self-consistent oxide tunneling model has been used for device simulation, which is simple to implement and assist in the study of deep sub-micron MOS gate current effects, therefore correctly calculate the terminal current. Tunnel resistivity is also evaluated utilizing this tunneling current density model. Theoretical predictions are compared with the results obtained by the 2-D numerical device simulator ATLAS, good agreements between the two are observed.

Gate Tunneling Current Predicting Model for Scaled NMOSFET Devices

2013 ◽  
Vol 772 ◽  
pp. 422-426
Author(s):  
Zhi Chao Zhao ◽  
Tie Feng Wu ◽  
Hui Bin Ma ◽  
Quan Wang ◽  
Jing Li
Keyword(s):  
Tunneling Current ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Integral Approach ◽  
Predicting Model ◽  
Mos Devices ◽  
Gate Oxide Thickness ◽  
Novel Theory ◽  
Gate Tunneling ◽  
Thin Gate Oxide

With the scaling of MOS devices, gate tunneling current increases significantly due to thinner gate oxides, and static characteristics of devices and circuit are severely affected by the presence of gate tunneling currents. In this paper, a novel theory gate tunneling current predicting model using integral approach is presented in ultra-thin gate oxide MOS devices that tunneling current changes with gate-oxide thickness. To analyze quantitatively the behaviors of scaled MOS devices in the effects of gate tunneling current and predict the trends, the characteristics of MOS devices are studied in detail using HSPICE simulator. The simulation results in BSIM4 model well agree with the model proposed. The theory and experiment data are contributed to the VLSI circuit design in the future.

Characterization of Graphene Gate Electrodes for Metal-Oxide-Semiconductor Devices

MRS Advances ◽  
2017 ◽  
Vol 2 (02) ◽  
pp. 103-108 ◽  
Author(s):  
Yanbin An ◽  
Aniruddh Shekhawat ◽  
Ashkan Behnam ◽  
Eric Pop ◽  
Ant Ural
Keyword(s):  
Metal Oxide ◽  
High Frequency ◽  
Tunneling Current ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Heterogeneous Integration ◽  
Gate Electrodes ◽  
Mos Devices ◽  
Capacitance Voltage

ABSTRACT We fabricate and characterize metal-oxide-semiconductor (MOS) devices with graphene as the gate electrode, 5 or 10 nm thick silicon dioxide as the insulator, and silicon as the semiconductor substrate. We find that Fowler-Nordheim tunneling dominates the gate current for the 10 nm oxide device. We also study the temperature dependence of the tunneling current in these devices in the range 77 to 300 K and extract the effective tunneling barrier height as a function of temperature for the 10 nm oxide device. Furthermore, by performing high frequency capacitance-voltage measurements, we observe a local capacitance minimum under accumulation, particularly for the 5 nm oxide device. By fitting the data using numerical simulations based on the modified density of states of graphene in the presence of charged impurities, we show that this local minimum results from the quantum capacitance of graphene. These results provide important insights for the heterogeneous integration of graphene into conventional silicon technology.

scholarly journals A Quantitative Analysis of Tunneling Current in A MOS Cell for A Low-Voltage Microcontroller

1998 ◽  
Vol 20 (3) ◽  
pp. 165-167 ◽  
Author(s):  
M. A. Grado-Caffaro ◽  
M. Grado-Caffaro
Keyword(s):  
Quantitative Analysis ◽  
Current Density ◽  
Low Voltage ◽  
Tunneling Current ◽  
Approximate Expression ◽  
Oxide Thickness ◽  
Charge Carriers

The tunneling current density in a MOS cell for a low-voltage microcontroller based on EEPROM is calculated for high electric strengths. Furthermore, this current density is discussed in terms of the oxide thickness and an approximate expression for the velocity of charge carriers is derived.

A tunneling current density model for ultra thin HfO2 high-k dielectric material based MOS devices

2016 ◽  
Vol 95 ◽  
pp. 24-32 ◽  
Author(s):  
Niladri Pratap Maity ◽  
Reshmi Maity ◽  
R.K. Thapa ◽  
Srimanta Baishya
Keyword(s):  
Current Density ◽  
Dielectric Material ◽  
Tunneling Current ◽  
Density Model ◽  
Mos Devices ◽  
High K ◽  
High K Dielectric

Fowler-Nordheim Tunneling Current Oscillation Study of Interface Roughness

1999 ◽  
Vol 567 ◽  
Author(s):  
L. Lai ◽  
E.A. Irene
Keyword(s):  
Fractal Dimension ◽  
Oscillation Amplitude ◽  
Tunneling Current ◽  
Interface Roughness ◽  
Oxide Semiconductor ◽  
Spatial Complexity ◽  
Force Microscopy ◽  
Mos Devices ◽  
Atomic Force ◽  
Amplitude Decrease

ABSTRACTA decrease in the amplitude of Fowler-Nordheim current oscillations (FN-CO) due to interface roughness is observed for thin film (∼40Å) metal-oxide-semiconductor (MOS) devices, only when the interface has high spatial complexity. Previous studies have shown no measurable changes in FN-CO's resulting from the oxidation of purposely roughened Si surfaces. The present research continues with an FN-CO study using Si surfaces with roughness of higher spatial complexity than the previous studies. The spatial complexity of the purposely roughened Si surfaces was compared using the fractal dimension (DF). Atomic force microscopy (AFM) was used to measure the interface topography, and fractal dimension (DF) was used to describe the surface complexity while root-mean-square (RMS) roughness was used for obtaining vertical information of the roughness. It was found that the oscillation amplitude decrease substantially with an increase of DF but with no dependence on RMS.

Analysis of Interface Trap Densities for Al2O3 Dielectric Material Based Ultra Thin MOS Devices

2016 ◽  
Vol 860 ◽  
pp. 25-29 ◽  
Author(s):  
Niladri Pratap Maity ◽  
Rajiv R. Thakur ◽  
Reshmi Maity ◽  
R.K. Thapa ◽  
S. Baishya
Keyword(s):  
Dielectric Material ◽  
Oxide Thickness ◽  
Oxide Semiconductor ◽  
Interface Trap ◽  
Mos Devices ◽  
Novel Approach ◽  
High K ◽  
Conductance Method ◽  
High K Dielectric ◽  
P Type

In this paper the interface trap densities (Dit) are analyzed for ultra thin dielectric material based metal oxide semiconductor (MOS) devices using high-k dielectric material Al2O3. The Dit have been calculated by a novel approach using conductance method and it indicates that by reducing the thickness of the oxide, the Dit increases and similar increase is also found by replacing SiO2 with Al2O3. For the same oxide thickness SiO2 has the lowest Dit and found to be the order of 1011 cm-2eV-1. The Dit is found to be in good agreement with published fabrication results at p-type doping level of 1 × 1017 cm-3. Numerical calculations and solutions are performed by MATLAB and device simulation is done by ATLAS.

The Effect of Roughness Features on Mos Surface Electric Field and Fowler-Nordheim Tunneling Behavior

1997 ◽  
Vol 473 ◽  
Author(s):  
Heng-Chih Lin ◽  
Edwin C. Kan ◽  
Toshiaki Yamanaka ◽  
Simon J. Fang ◽  
Kwame N. Eason ◽  
...  
Keyword(s):  
Electric Field ◽  
Three Dimensional ◽  
Tunneling Current ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Interface Roughness ◽  
Normal Electric Field ◽  
Surface Electric Field ◽  
Tunneling Behavior ◽  
Nordheim Tunneling

ABSTRACTFor future CMOS GSI technology, Si/SiO2 interface micro-roughness becomes a non-negligible problem. Interface roughness causes fluctuations of the surface normal electric field, which, in turn, change the gate oxide Fowler-Nordheim tunneling behavior. In this research, we used a simple two-spheres model and a three-dimensional Laplace solver to simulate the electric field and the tunneling current in the oxide region. Our results show that both quantities are strong functions of roughness spatial wavelength, associated amplitude, and oxide thickness. We found that RMS roughness itself cannot fully characterize surface roughness and that roughness has a larger effect for thicker oxide in terms of surface electric field and tunneling behavior.

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