Drain Current Modeling of Tunnel FET using Simpson’s Rule

Tunnel Field Effect Transistor can be introduced as an emerging alternate to MOSFET which is energy efficient and can be used in low power applications. Due to the challenge involved in integration of band to band tunneling generation rate, the existing drain current models are inaccurate. A compact analytical model for simple tunnel FET and pnpn tunnel FET is proposed which is highly accurate. The numerical integration of tunneling generation rate in the tunneling region is performed using Simpson’s rule. Integration is done using both Simpson’s 1/3 rule and 3/8 rule and the models are validated against numerical device simulations. The models are compared with existing models and it is observed that the proposed models show excellent agreement with device simulations in the entire region of operation with Simpson’s 3/8 rule exhibiting the maximum accuracy.

Improved DC Performance Analysis of a Novel Asymmetric Extended Source Tunnel FET for Fast Switching Application

A two-dimensional analytical model for asymmetric extended source tunnel field effect transistor (AES-TFET) has been developed to obtain better device performance. The proposed device model has been analytically modelled and performed by solving 2-D Poisson’s equation. Surface potential distribution, electric field variation and band-to-band tunneling (BTBT) rate have been investigated by this numerical modelling. The source region of novel structure of TFET has been extended (varied 2 nm to 6 nm) to incorporate corner effect, which allows BTBT through a thin tunneling barrier, with controlled ambipolar conduction. This eventually produces better source-channel interface tunneling for a n-channel AES-TFET. 2-D numerical device simulator (SILVACO TCAD) has been used for simulation work. The simulated work has been finally validated by analytical modelling of AES-TFET. Better ION, IOFF and switching ratio has been obtained from this novel TFET structure.

Physics Based Analytical Modeling of Asymmetric Elevated Source Tunnel FET (AES-TFET) for Better Tunnel Junction Device (TJD) Performance

In this paper, a two-dimensional analytical model for asymmetric elevated source tunnel field effect transistor (AES-TFET) has been developed to obtain better tunnel junction device performance. Device physics based analytical modelling is performed by solving 2-D Poisson’s equation. Surface potential distribution, electric field variation and band-to-band tunneling (B2B) rate have been investigated by this numerical modelling. In our proposed structure, the source has been elevated (varied 2 nm to 6 nm) to incorporate corner effect; which boosts the carrier transport via thin tunneling barrier, with controlled ambipolar conduction. This eventually produces better source-channel interface tunneling for a n-channel AES-TFET structure. 2-D numerical device simulator (SILVACO TCAD) has been used for simulation work. The simulated graphical representations have been finally validated by analytical modelling of AES-TFET.

Semiconductor Device Modeling and Simulation for Electronic Circuit Design

This chapter covers different methods of semiconductor device modeling for electronic circuit simulation. It presents a discussion on physics-based analytical modeling approach to predict device operation at specific conditions such as applied bias (e.g., voltages and currents); environment (e.g., temperature, noise); and physical characteristics (e.g., geometry, doping levels). However, formulation of device model involves trade-off between accuracy and computational speed and for most practical operation such as for SPICE-based circuit simulator, empirical modeling approach is often preferred. Thus, this chapter also covers empirical modeling approaches to predict device operation by implementing mathematically fitted equations. In addition, it includes numerical device modeling approaches, which involve numerical device simulation using different types of commercial computer-based tools. Numerical models are used as virtual environment for device optimization under different conditions and the results can be used to validate the simulation models for other operating conditions.

Ambipolar Reduction Methodology for SOI Tunnel FETs in Low Power Applications: A Performance Report

Continuous device scaling of tunnel field effect transistors (TFET) faces real challenges in low power VLSI applications. Here in this article, the major limitation of TFET i.e. Ambipolar conduction behavior has been thoroughly discussed and remedies to suppress the leakage current (IOFF) has also been investigated. A thin pocket layers is incorporated in source and drain regions separately at Silicon on Insulator (SOI) TFET, keeping supply voltage (VDD) at 0.5 V. The detail analytical modeling of surface potential distribution along the channel, electric field and tunneling current is derived in this paper. Using two-dimensional numerical device simulator, the various designs are modeled and validated with our proposed methodology. Non-local Band-to-Band tunneling (BTBT) is used for simulation purpose. It is observed that a drain pocket actually helps to reduce the ambipolar conduction and provide better drive current (ION) for fast switching. This further improves the ION/IOFF ratio and also results better subthreshold swing (SS) as 27.43mV/decade to optimize the device characteristics.

TCAD SIMULATION AND PERFORMANCE ANALYSIS OF SINGLE AND DUAL GATE OTFTs

This paper presents finite element-based numerical simulation and performance analysis of dual and single gate pentacene-based organic thin film transistors (OTFTs) using technology computer-aided design (TCAD) tools. Electrical characteristics of the devices have been simulated using 2D numerical device simulation software ATLAS™ from Silvaco International. Also, device parameters like threshold voltage, mobility, transconductance, subthreshold swing and current on/off ratio of the single and dual gate OTFTs have been extracted and compared.

Design, Fabrication and Characterization of a 4.5kV / 50A 4H-SiC PiN Rectifiers

In this work, a 4.5kV/50A 4H-SiC PiN rectifiers with mesa combined with double-JTE structures is successfully developed for high power applications. Two-dimension numerical device simulator Silvaco-TCAD is applied to optimizing the electrical performance of fabricated rectifiers. Mesa-combined double-JTE structure is utilized to achieve a high blocking voltage with a wider optimum process latitude. A forward current is 50 A at room temperature when SiC PiN device bias 4.1 V, while the maximum blocking voltage achieved is 4.7 kV, reaching up to 86% of parallel-plane junction bulk breakdown.