A computationally efficient compact model for fully-depleted SOI MOSFETs with independently-controlled front- and back-gates

2011 ◽  
Vol 62 (1) ◽  
pp. 31-39 ◽  
Author(s):  
Darsen D. Lu ◽  
Mohan V. Dunga ◽  
Chung-Hsun Lin ◽  
Ali M. Niknejad ◽  
Chenming Hu
2022 ◽  
Author(s):  
Shubham Sahay ◽  
Amol Gaidhane ◽  
Yogesh Singh Chauhan ◽  
Raghvendra Dangi ◽  
Amit Verma

<div>In this paper, we develop a Verilog-A implementable compact model for the dynamic switching of ferroelectric Fin-FETs (Fe-FinFETs) for asymmetric non-periodic input signals. We use the multi-domain Preisach Model to capture the saturated P-E loop of the ferroelectric capacitors. In addition to the saturation loop, we model the history dependent minor loop paths in the P-E by tracing input signals’ turning points. To capture the input signals’ turning points, we propose an R-C circuit based approach in this work. We calibrate our proposed model with the experimental data, and it accurately captures the history effect and minor loop paths of the ferroelectric capacitor. Furthermore, the elimination of storage of each turning point makes the proposed model computationally efficient compared with the previous implementations. We also demonstrate the unique electrical characteristics of Fe-FinFETs by integrating the developed compact model of Fe-Cap with the BSIM-CMG model of 7nm FinFET.</div>


2022 ◽  
Author(s):  
Shubham Sahay ◽  
Amol Gaidhane ◽  
Yogesh Singh Chauhan ◽  
Raghvendra Dangi ◽  
Amit Verma

<div>In this paper, we develop a Verilog-A implementable compact model for the dynamic switching of ferroelectric Fin-FETs (Fe-FinFETs) for asymmetric non-periodic input signals. We use the multi-domain Preisach Model to capture the saturated P-E loop of the ferroelectric capacitors. In addition to the saturation loop, we model the history dependent minor loop paths in the P-E by tracing input signals’ turning points. To capture the input signals’ turning points, we propose an R-C circuit based approach in this work. We calibrate our proposed model with the experimental data, and it accurately captures the history effect and minor loop paths of the ferroelectric capacitor. Furthermore, the elimination of storage of each turning point makes the proposed model computationally efficient compared with the previous implementations. We also demonstrate the unique electrical characteristics of Fe-FinFETs by integrating the developed compact model of Fe-Cap with the BSIM-CMG model of 7nm FinFET.</div>


2021 ◽  
Vol 11 (23) ◽  
pp. 11088
Author(s):  
Djeber Guendouz ◽  
Chhandak Mukherjee ◽  
Marina Deng ◽  
Magali De Matos ◽  
Christophe Caillaud ◽  
...  

Due to the continuous increase in data traffic, it is becoming imperative to develop communication systems capable of meeting the throughput requirements. Monolithic Opto-Electronic Integrated Circuits (OEICs) are ideal candidates to meet these demands. With that in mind, we propose a compact and computationally efficient model for Uni-Traveling Carrier Photodiodes (UTC-PDs) which are a key component of OEICs because of their high bandwidth and RF output power. The developed compact model is compatible with existing SPICE design software, enabling the design of beyond 5G and terahertz (THz) communication circuits and systems. By introducing detailed physical equations describing, in particular, the dark current, the intrinsic series resistance, and the junction capacitance, the model accurately captures the physical characteristics of the UTC-PD. The model parameter extraction follows a scalable extraction methodology derived from that of the bipolar and CMOS technologies. A detailed description of the de-embedding process is presented. Excellent agreement between the compact model and measurements has been achieved, showing model versatility across various technologies and scalability over several geometries.


2020 ◽  
Vol 35 (4) ◽  
pp. 045007
Author(s):  
Afiq Hamzah ◽  
N Ezaila Alias ◽  
Michael Loong Peng Tan ◽  
Ali Hosseingholipourasl ◽  
Razali Ismail

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