A review of the mechanical stressors efficiency applied to the ultra-thin body & buried oxide fully depleted silicon on insulator technology

2016 ◽  
Vol 117 ◽  
pp. 100-116 ◽  
Author(s):  
Pierre Morin ◽  
Sylvain Maitrejean ◽  
Frederic Allibert ◽  
Emmanuel Augendre ◽  
Qing Liu ◽  
...  
Keyword(s):  
Silicon On Insulator ◽  
Thin Body ◽  
Fully Depleted ◽  
Buried Oxide ◽  
Silicon On Insulator Technology

Advantages of Faceted P-Raised Source/Drain in Fully Depleted Silicon on Insulator Technology

2018 ◽  
Vol 86 (7) ◽  
pp. 199-206 ◽  
Author(s):  
Ömür Işıl Aydin ◽  
Judson Robert Holt ◽  
Cyrille Le Royer ◽  
Laks Vanamurthy ◽  
Thomas Feudel ◽  
...  
Keyword(s):  
Silicon On Insulator ◽  
Fully Depleted ◽  
Silicon On Insulator Technology

Fabrication and Electrical Characterization of Ultra-Thin Body and BOX (UTBB) Back Enhanced SOI (BESOI) pMOSFET

2020 ◽  
Vol 15 (1) ◽  
pp. 1-6
Author(s):  
Ricardo Cardoso Rangel ◽  
Katia R. A. Sasaki ◽  
Leonardo Shimizu Yojo ◽  
João Antonio Martino
Keyword(s):  
First Generation ◽  
Electrical Characterization ◽  
Current Drive ◽  
The Body ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Thin Body ◽  
Back Gate ◽  
Buried Oxide ◽  
Complementary Mos Technology

This work analyzes the third generation BESOI MOSFET (Back-Enhanced Silicon-On-Insulator Metal-Oxide-Semiconductor Field-Effect-transistor) built on UTBB (Ultra-Thin Body and Buried Oxide), comparing it to the BESOI with thick buried oxide (first generation). The stronger coupling between front and back interfaces of the UTBB BESOI device improves in 67% the current drive, 122% the maximum transconductance and 223% the body factor. Operating with seven times lower back gate bias, the UTBB BESOI MOSFET presented more compatibility with standard SOI CMOS (Complementary MOS) technology than the BESOI with thick buried oxide.

Study and Reduction of Variability in 28 nm Fully Depleted Silicon on Insulator Technology

2016 ◽  
Vol 12 (1) ◽  
pp. 64-73 ◽  
Author(s):  
Zhaopeng Wei ◽  
Gilles Jacquemod ◽  
Philippe Lorenzini ◽  
Frederic Hameau ◽  
Emeric de Foucauld ◽  
...  
Keyword(s):  
Silicon On Insulator ◽  
Fully Depleted ◽  
Silicon On Insulator Technology ◽  
28 Nm

X-band receiver module in fully depleted silicon on insulator technology

2012 ◽  
Author(s):  
A. Mattamana ◽  
K. Groves ◽  
P. Orlando ◽  
V. J. Patel ◽  
T. Quach ◽  
...  
Keyword(s):  
Silicon On Insulator ◽  
Fully Depleted ◽  
X Band ◽  
Receiver Module ◽  
Silicon On Insulator Technology

Ultra-thin body & buried oxide SOI substrate development and qualification for Fully Depleted SOI device with back bias capability

2016 ◽  
Vol 117 ◽  
pp. 2-9 ◽  
Author(s):  
Walter Schwarzenbach ◽  
Bich-Yen Nguyen ◽  
Frederic Allibert ◽  
Christophe Girard ◽  
Christophe Maleville
Keyword(s):  
Thin Body ◽  
Fully Depleted ◽  
Buried Oxide

Towards High-Voltage MOSFETs in Ultrathin FDSOI

2016 ◽  
Vol 25 (01n02) ◽  
pp. 1640005 ◽  
Author(s):  
Antoine Litty ◽  
Sylvie Ortolland ◽  
Dominique Golanski ◽  
Christian Dutto ◽  
Alexandres Dartigues ◽  
...  
Keyword(s):  
High Voltage ◽  
Low Voltage ◽  
Ground Plane ◽  
Silicon Film ◽  
Silicon On Insulator ◽  
Drift Region ◽  
Back Gate ◽  
Fully Depleted ◽  
Buried Oxide ◽  
Core Technology

High-Voltage MOSFETs are essential devices for complementing and extending the domains of application of any core technology including low-power, low-voltage CMOS. In this paper, we propose and describe advanced Extended-Drain MOSFETs, designed, processed and characterized in ultrathin body and buried oxide Fully Depleted Silicon on Insulator technology (UTBB-FDSOI). These transistors have been implemented in two technology nodes (28 nm and 14 nm) with different silicon film and buried oxide thicknesses (TSi < 10nm and TBOX ≤ 25nm). Our innovative concept of Dual Ground Plane (DGP) provides RESURF-like effect (reduced surface field) and offers additional flexibility for HVMOS integration directly in the ultrathin film of the FDSOI wafer. In this configuration, the primary back-gate controls the threshold voltage (VTH) to ensure performance and low leakage current. The second back-gate, located underneath the drift region, acts as a field plate enabling the improvement of the ON resistance (RON) and breakdown voltage (BV). The trade-off RON.S versus BV is investigated as a function of doping level, length and thickness of the drift region. We report promising results and discuss further developments for successful integration of high-voltage MOSFETs in ultrathin CMOS FDSOI technology.

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