Study and Reduction of Variability in 28 nm Fully Depleted Silicon on Insulator Technology

2016 ◽  
Vol 12 (1) ◽  
pp. 64-73 ◽  
Author(s):  
Zhaopeng Wei ◽  
Gilles Jacquemod ◽  
Philippe Lorenzini ◽  
Frederic Hameau ◽  
Emeric de Foucauld ◽  
...  
Keyword(s):  
Silicon On Insulator ◽  
Fully Depleted ◽  
Silicon On Insulator Technology ◽  
28 Nm

Advantages of Faceted P-Raised Source/Drain in Fully Depleted Silicon on Insulator Technology

2018 ◽  
Vol 86 (7) ◽  
pp. 199-206 ◽  
Author(s):  
Ömür Işıl Aydin ◽  
Judson Robert Holt ◽  
Cyrille Le Royer ◽  
Laks Vanamurthy ◽  
Thomas Feudel ◽  
...  
Keyword(s):  
Silicon On Insulator ◽  
Fully Depleted ◽  
Silicon On Insulator Technology

A 31 GHz body-biased configurable power amplifier in 28 nm FD-SOI CMOS for 5 G applications

2020 ◽  
pp. 1-18
Author(s):  
Florent Torres ◽  
Eric Kerhervé ◽  
Andreia Cathelin ◽  
Magali De Matos
Keyword(s):  
Power Amplifier ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Fully Depleted ◽  
Technology Roadmap ◽  
Wide Range ◽  
28 Nm ◽  
Soi Cmos

Abstract This paper presents a 31 GHz integrated power amplifier (PA) in 28 nm Fully Depleted Silicon-On-Insulator Complementary Metal Oxide Semiconductor (FD-SOI CMOS) technology and targeting SoC implementation for 5 G applications. Fine-grain wide range power control with more than 10 dB tuning range is enabled by body biasing feature while the design improves voltage standing wave ratio (VSWR) robustness, stability and reverse isolation by using optimized 90° hybrid couplers and capacitive neutralization on both stages. Maximum power gain of 32.6 dB, PAEmax of 25.5% and Psat of 17.9 dBm are measured while robustness to industrial temperature range and process spread is demonstrated. Temperature-induced performance variation compensation, as well as amplitude-to-phase modulation (AM-PM) optimization regarding output power back-off, are achieved through body-bias node. This PA exhibits an International Technology Roadmap for Semiconductors figure of merit (ITRS FOM) of 26 925, the highest reported around 30 GHz to authors' knowledge.

A review of the mechanical stressors efficiency applied to the ultra-thin body & buried oxide fully depleted silicon on insulator technology

2016 ◽  
Vol 117 ◽  
pp. 100-116 ◽  
Author(s):  
Pierre Morin ◽  
Sylvain Maitrejean ◽  
Frederic Allibert ◽  
Emmanuel Augendre ◽  
Qing Liu ◽  
...  
Keyword(s):  
Silicon On Insulator ◽  
Thin Body ◽  
Fully Depleted ◽  
Buried Oxide ◽  
Silicon On Insulator Technology

Energy Study for 28 nm Fully Depleted Silicon-On-Insulator Devices

2016 ◽  
Vol 12 (1) ◽  
pp. 58-63
Author(s):  
Rida Kheirallah ◽  
Gilles Ducharme ◽  
Nadine Azemard
Keyword(s):  
Silicon On Insulator ◽  
Fully Depleted ◽  
28 Nm

X-band receiver module in fully depleted silicon on insulator technology

2012 ◽  
Author(s):  
A. Mattamana ◽  
K. Groves ◽  
P. Orlando ◽  
V. J. Patel ◽  
T. Quach ◽  
...  
Keyword(s):  
Silicon On Insulator ◽  
Fully Depleted ◽  
X Band ◽  
Receiver Module ◽  
Silicon On Insulator Technology

Planar Fully-Depleted-Silicon-On-Insulator technologies: Toward the 28 nm node and beyond

2016 ◽  
Vol 117 ◽  
pp. 37-59 ◽  
Author(s):  
B. Doris ◽  
B. DeSalvo ◽  
K. Cheng ◽  
P. Morin ◽  
M. Vinet
Keyword(s):  
Silicon On Insulator ◽  
Fully Depleted ◽  
28 Nm

Integration of diamond in fully-depleted silicon-on-insulator technology as buried insulator: A theoretical analysis

2008 ◽  
Vol 17 (7-10) ◽  
pp. 1248-1251 ◽  
Author(s):  
Jean-Paul Mazellier ◽  
Olivier Faynot ◽  
Sorin Cristoloveanu ◽  
Simon Deleonibus ◽  
Philippe Bergonzo
Keyword(s):  
Theoretical Analysis ◽  
Silicon On Insulator ◽  
Fully Depleted ◽  
Silicon On Insulator Technology

scholarly journals High-Speed Serializer for a 64 GS s<sup>−1</sup> Digital-to-Analog Converter in a 28 nm Fully-Depleted Silicon-on-Insulator CMOS Technology

2018 ◽  
Vol 16 ◽  
pp. 99-108
Author(s):  
Daniel Widmann ◽  
Markus Grözing ◽  
Manfred Berroth
Keyword(s):  
High Speed ◽  
Average Power ◽  
Silicon On Insulator ◽  
Output Stage ◽  
Fully Depleted ◽  
Data Rates ◽  
Average Power Consumption ◽  
Digital To Analog ◽  
On Chip ◽  
28 Nm

Abstract. An attractive solution to provide several channels with very high data rates of tens of Gbit s−1 for digital-to-analog converters (DACs) in arbitrary waveform generators (AWGs) is to use a high speed serializer in front of the DAC. As data sources, on-chip memories, digital signal processors or field-programmable gate arrays can be used. Here, we present a serializer consisting of a 19 channel 16:1 multiplexer (MUX) for output data rates up to 64 Gbit s−1 per channel and a low skew (∼ 8.8 ps) two-phase frequency divider and clock distribution network that is completely realized in static CMOS logic. The circuit is designed in a 28 nm Fully-Depleted Silicon-on-Insulator (FD-SOI) technology and will be used in an 8 bit 64 GS s−1 DAC between the on-chip memory and the DAC output stage. Due to a four bits unary and four bits binary segmentation, a 19 channel MUX is required. Simulations on layout level reveal a data-dependent peak-to-peak jitter of less than 1.8 ps at the output of one MUX channel with a total average power consumption of approximately 1.15 W of the whole MUX and clock network.

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