Until recently, power semiconductors were usually produced as TO, power-PAK, and D-PAK style packaging, due to die size, thermal dissipation requirements, and the vertical flow of current through the devices. The introduction of GaN to power semiconductors has allowed manufactures to produce devices with approximately 9% the footprint of similar rated D-PAK Si MOSFETs. In addition, GaN semiconductors have much better theoretical limits of specific on-resistance to breakdown voltage, when compared to Si and SiC. As of now, GaN devices offer very good performance at much less the cost of SiC, very small footprints, no reverse recovery losses of a body diode, very low RDS(ON), and very fast turn-on and turn-off times due to QGS in single-digit nC range. GaN semiconductors are expected to make vast improvements over the next decade. Unfortunately, this decrease in package size has made design prototyping significantly more challenging. Traditional manual solder iron assembly is not sufficient for these devices. Difficulties include board design, device handling, alignment, solder reflow, flux residue removal, and post-assembly inspection. The EPC 2014 and 2015 devices both have a 4mm pitch and are 1.85mm2 and 6.70mm2, respectively. In many situations, the decreased pitch and small overall size of these devices mandate the use of automated assembly equipment, such as a pick & place, to ensure quality and repeatability of assembly. However, this may not be feasible for initial prototyping, due to cost and time constraints. Here we will present a technique for manual assembly of these chip scale devices, applied specifically to the EPC 2014 and 2015. This should decrease the cost and turn time for prototype assembly when utilizing these types of chip scale packaged power semiconductor devices.
Cheaper and smaller or more expensive and larger: how consumers respond to unit price increase tactics that simultaneously change product price and package size
