Tin–lead (SnPb) solder reaction in flip chip technology

2001 ◽  
Vol 34 (1) ◽  
pp. 1-58 ◽  
Author(s):  
K.N Tu ◽  
K Zeng
1999 ◽  
Vol 85 (12) ◽  
pp. 8456-8463 ◽  
Author(s):  
J. W. Jang ◽  
P. G. Kim ◽  
K. N. Tu ◽  
D. R. Frear ◽  
P. Thompson

Author(s):  
Annie T. Huang ◽  
Chung-Kuang Chou ◽  
Chih Chen

This paper reports an easy, low cost, and low temperature hermetic packaging technology utilizing eutectic SnPb solder and Cr/Ni/Cu bonding pad. We investigate the bonding results of silicon-silicon as well as silicon-glass and glass-glass bonding. Most hermetic packaging technologies require a bonding temperature higher than 300°C. Because some devices are sensitive to temperature that decreases their functionalities, two localized heating technology have been proposed. One technology generates heat via built-in-microheaters on the silicon substrate. Another localized heating technology utilizes microwave as a heating source [1]. However, both technologies require high cost and cannot be implemented for mass production. Furthermore, local heating creates a large temperature gradient. The stress causes crack on the substrates, thus limiting the selection of substrate materials. We choose eutectic tin-lead with the melting temperature of 183°C. Metal thin films we choose is also similar to the under bump metallurgy used for flip chip technology. The advantage of solder is its metal property. With a width of a few micrometers, metal can block moisture for over a decade. In addition, solder is known to pertain self-aligning property in flip chip technology. Other kind of solders can also be applied for hermetic packaging as well. Shie et al have tested In-Sn as bonding using the reflow temperature as low as 120 °C [2]. Seong-A Kim et. al have tested Au-Sn solder line at 400°C [3,4]. Due to the difference in melting points, the application of Sn-Pb, Au-Sn and In-Sn can be different. Bonding characteristic of our design is investigated on three different setups: silicon-silicon, silicon-glass, and glass-glass samples. (Fig.1) This experiment consists of three different setups: silicon-to-silicon bonding, silicon-to-glass bonding, and glass-to-glass bonding. These three different setups utilize the same bonding method. The design includes square patterns and circle patterns of 500 μm width as shown in Figure 2. Schematic process flow of sample fabrication is demonstrated in Figure 3. Substrate and cap have identical size with the pattern of square of 1 cm in width or circle of 1 cm in diameter. The bonding pad is composed of three layers of metal from bottom to top: 500 Å of chromium, 2000 Å of nickel and 6000 Å of copper.(Fig.3b) Eutectic SnPb solder is reflowed on square or circle patterns on a hot plate at room ambient.(Fig.3d) Sample pairs are then bonded on a hot plate at 200°C for about 1.5 minutes for silicon-silicon and silicon glass bonding and 3 minutes for glass-glass bonding.(Fig.3e) Before placing the sample pairs on the hot plate, for glass-glass and glass-silicon bonding, we align a pair of chips of matched pattern by visual alignment. For silicon-silicon bonding, we align two chips along the dividing lines. Figure 4a and 4b show a glass and a silicon sample after solder reflow respectively. Sample pairs after bonding process are seen in Figure 5a through 5c. Figures 6a through 6c show the cross-sectional picture of the joint. Figures 6b and 6c are enlarged pictures of left and right side of the joints respectively. The average misalignment is 11.2 μm and 13.6 μm for square and circle samples respectively. Bonding strength of the three setups ranges from 3 MPa to 10 MPa. For leakage rate test, a 3 mm hole in diameter was drilled under the sealed area on the substrate side, followed by connecting a glass pipe to the hole by frit glass. The setup can be pumped down to the order of 10−8 torr.


2001 ◽  
Vol 89 (6) ◽  
pp. 3189-3194 ◽  
Author(s):  
T. Y. Lee ◽  
K. N. Tu ◽  
S. M. Kuo ◽  
D. R. Frear

Author(s):  
Andrew J. Komrowski ◽  
N. S. Somcio ◽  
Daniel J. D. Sullivan ◽  
Charles R. Silvis ◽  
Luis Curiel ◽  
...  

Abstract The use of flip chip technology inside component packaging, so called flip chip in package (FCIP), is an increasingly common package type in the semiconductor industry because of high pin-counts, performance and reliability. Sample preparation methods and flows which enable physical failure analysis (PFA) of FCIP are thus in demand to characterize defects in die with these package types. As interconnect metallization schemes become more dense and complex, access to the backside silicon of a functional device also becomes important for fault isolation test purposes. To address these requirements, a detailed PFA flow is described which chronicles the sample preparation methods necessary to isolate a physical defect in the die of an organic-substrate FCIP.


Author(s):  
O. Diaz de Leon ◽  
M. Nassirian ◽  
C. Todd ◽  
R. Chowdhury

Abstract Integration of circuits on semiconductor devices with resulting increase in pin counts is driving the need for improvements in packaging for functionality and reliability. One solution to this demand is the Flip- Chip concept in Ultra Large Scale Integration (ULSI) applications [1]. The flip-chip technology is based on the direct attach principle of die to substrate interconnection.. The absence of bondwires clearly enables packages to become more slim and compact, and also provides higher pin counts and higher-speeds [2]. However, due to its construction, with inherent hidden structures the Flip-Chip technology presents a challenge for non-destructive Failure Analysis (F/A). The scanning acoustic microscope (SAM) has recently emerged as a valuable evaluation tool for this purpose [3]. C-mode scanning acoustic microscope (C-SAM), has the ability to demonstrate non-destructive package analysis while imaging the internal features of this package. Ultrasonic waves are very sensitive, particularly when they encounter density variations at surfaces, e.g. variations such as voids or delaminations similar to air gaps. These two anomalies are common to flip-chips. The primary issue with this package technology is the non-uniformity of the die attach through solder ball joints and epoxy underfill. The ball joints also present defects as open contacts, voids or cracks. In our acoustic microscopy study packages with known defects are considered. It includes C-SCAN analysis giving top views at a particular package interface and a B-SCAN analysis that provides cross-sectional views at a desired point of interest. The cross-section analysis capability gives confidence to the failure analyst in obtaining information from a failing area without physically sectioning the sample and destroying its electrical integrity. Our results presented here prove that appropriate selection of acoustic scanning modes and frequency parameters leads to good reliable correlation between the physical defects in the devices and the information given by the acoustic microscope.


2021 ◽  
Vol 11 (15) ◽  
pp. 7057
Author(s):  
Lin Wang ◽  
Zhe Cheng ◽  
Zhi-Guo Yu ◽  
De-Feng Lin ◽  
Zhe Liu ◽  
...  

Half-bridge modules with integrated GaN high electron mobility transistors (HEMTs) and driver dies were designed and fabricated in this research. Our design uses flip-chip technology for fabrication, instead of more generally applied wire bonding, to reduce parasitic inductance in both the driver-gate and drain-source loops. Modules were prepared using both methods and the double-pulse test was applied to evaluate and compare their switching characteristics. The gate voltage (Vgs) waveform of the flip-chip module showed no overshoot during the turn-on period, and a small oscillation during the turn-off period. The probabilities of gate damage and false turn-on were greatly reduced. The inductance in the drain-source loop of the module was measured to be 3.4 nH. The rise and fall times of the drain voltage (Vds) were 12.9 and 5.8 ns, respectively, with an overshoot of only 4.8 V during the turn-off period under Vdc = 100 V. These results indicate that the use of flip-chip technology along with the integration of GaN HEMTs with driver dies can effectively reduce the parasitic inductance and improve the switching performance of GaN half-bridge modules compared to wire bonding.


Author(s):  
Peian Li ◽  
Xu Zhang ◽  
Wing Cheung Chong ◽  
Kei May Lau

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