scholarly journals A spiking and adapting tactile sensor for neuromorphic applications

2020 ◽  
Vol 10 (1) ◽  
Author(s):  
Tom Birkoben ◽  
Henning Winterfeld ◽  
Simon Fichtner ◽  
Adrian Petraru ◽  
Hermann Kohlstedt

Abstract The ongoing research on and development of increasingly intelligent artificial systems propels the need for bio inspired pressure sensitive spiking circuits. Here we present an adapting and spiking tactile sensor, based on a neuronal model and a piezoelectric field-effect transistor (PiezoFET). The piezoelectric sensor device consists of a metal-oxide semiconductor field-effect transistor comprising a piezoelectric aluminium-scandium-nitride (AlxSc1−xN) layer inside of the gate stack. The so augmented device is sensitive to mechanical stress. In combination with an analogue circuit, this sensor unit is capable of encoding the mechanical quantity into a series of spikes with an ongoing adaptation of the output frequency. This allows for a broad application in the context of robotic and neuromorphic systems, since it enables said systems to receive information from the surrounding environment and provide encoded spike trains for neuromorphic hardware. We present numerical and experimental results on this spiking and adapting tactile sensor.

2021 ◽  
Vol 5 (1) ◽  
Author(s):  
Aryan Afzalian

AbstractUsing accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10-nm scaling for high-performance complementary metal oxide semiconductor (CMOS) applications. We show that a combination of good electrostatic control together with high mobility is paramount to meet the stringent roadmap targets. Such requirements typically play against each other at sub-10-nm gate length for MOS transistors made of conventional semiconductor materials like Si, Ge, or III–V and dimensional scaling is expected to end ~12 nm gate-length (pitch of 40 nm). We demonstrate that using alternative 2D channel materials, such as the less-explored HfS2 or ZrS2, high-drive current down to ~6 nm is, however, achievable. We also propose a dynamically doped field-effect transistor concept, that scales better than its MOSFET counterpart. Used in combination with a high-mobility material such as HfS2, it allows for keeping the stringent high-performance CMOS on current and competitive energy-delay performance, when scaling down to virtually 0 nm gate length using a single-gate architecture and an ultra-compact design (pitch of 22 nm). The dynamically doped field-effect transistor further addresses the grand-challenge of doping in ultra-scaled devices and 2D materials in particular.


Materials ◽  
2021 ◽  
Vol 14 (13) ◽  
pp. 3554
Author(s):  
Jaeyeop Na ◽  
Jinhee Cheon ◽  
Kwangsoo Kim

In this paper, a novel 4H-SiC split heterojunction gate double trench metal-oxide-semiconductor field-effect transistor (SHG-DTMOS) is proposed to improve switching speed and loss. The device modifies the split gate double trench MOSFET (SG-DTMOS) by changing the N+ polysilicon split gate to the P+ polysilicon split gate. It has two separate P+ shielding regions under the gate to use the P+ split polysilicon gate as a heterojunction body diode and prevent reverse leakage `current. The static and most dynamic characteristics of the SHG-DTMOS are almost like those of the SG-DTMOS. However, the reverse recovery charge is improved by 65.83% and 73.45%, and the switching loss is improved by 54.84% and 44.98%, respectively, compared with the conventional double trench MOSFET (Con-DTMOS) and SG-DTMOS owing to the heterojunction.


1987 ◽  
Vol 65 (8) ◽  
pp. 995-998
Author(s):  
N. G. Tarr

It is shown that the accuracy of the charge-sheet model for the long-channel metal-oxide-semiconductor field-effect transistor can be improved by allowing for the small potential drop across the inversion layer, and by using a more accurate analytic approximation for the charge stored in the depletion region.


2008 ◽  
Vol 1144 ◽  
Author(s):  
Pranav Garg ◽  
Yi Hong ◽  
Md. Mash-Hud Iqbal ◽  
Stephen J. Fonash

ABSTRACTRecently, we have experimentally demonstrated a very simply structured unipolar accumulation-type metal oxide semiconductor field effect transistor (AMOSFET) using grow-in-place silicon nanowires. The AMOSFET consists of a single doping type nanowire, metal source and drain contacts which are separated by a partially gated region. Despite its simple configuration, it is capable of high performance thereby offering the potential of a low manufacturing-cost transistor. Since the quality of the metal/semiconductor ohmic source and drain contacts impacts AMOSFET performance, we repot here on initial exploration of contact variations and of the impact of thermal process history. With process optimization, current on/off ratios of 106 and subthreshold swings of 70 mV/dec have been achieved with these simple devices


2012 ◽  
Vol 100 (10) ◽  
pp. 101603 ◽  
Author(s):  
Seok-Ho Song ◽  
Hyun-Ho Yang ◽  
Chang-Hoon Han ◽  
Seung-Deok Ko ◽  
Seok-Hee Lee ◽  
...  

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