Charge trapping behavior visualization of dumbbell-shaped DSFXPY via electrical force microscopy

The electrons and holes are injected into the sterically hindered organic semiconductor film (DSFXPY, 1,6-di(spiro[fluorene-9,90-xanthene]-2-yl)pyrene) through applying controllable biases on the conductive atomic force microscopy tip.

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(Invited) Electrical Properties of Vapor-Deposited Organic Semiconductor Nanowires By Conductive Atomic Force Microscopy

ECS Meeting Abstracts ◽

10.1149/ma2020-01151054mtgabs ◽

2020 ◽

Vol MA2020-01 (15) ◽

pp. 1054-1054

Author(s):

Kwang-Won Park ◽

David Bilger ◽

Trisha L. Andrew

Keyword(s):

Atomic Force Microscopy ◽

Electrical Properties ◽

Organic Semiconductor ◽

Semiconductor Nanowires ◽

Conductive Atomic Force Microscopy ◽

Force Microscopy ◽

Atomic Force

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Post-stress/breakdown leakage mechanism in ultrathin high-κ (HfO2)x(SiO2)1-x/SiO2 gate stacks: A nanoscale conductive-Atomic Force Microscopy C-AFM

MRS Proceedings ◽

10.1557/proc-1108-a10-06 ◽

2008 ◽

Vol 1108 ◽

Author(s):

Hasan Javed Uppal ◽

Vladimir Markevich ◽

Stergios N Volkos ◽

Athanasios Dimoulas ◽

Bruce Hamilton ◽

...

Keyword(s):

Atomic Force Microscopy ◽

High Vacuum ◽

Charge Trapping ◽

Ultra High Vacuum ◽

Systematic Observation ◽

Gate Stacks ◽

Conductive Atomic Force Microscopy ◽

Force Microscopy ◽

Atomic Force ◽

Post Stress

AbstractConductive atomic force microscopy (C–AFM) in ultra high vacuum (UHV) has been used to characterize charge trapping in ultrathin as–deposited oxide films of 2–4 nm (HfO2)x(SiO2)1-x/SiO2 multilayer gate stacks. Pre– and post–stress/breakdown (BD) dielectric degradation is analyzed on a nanoscale. A systematic observation probes stress induced trap generation facilitating physical stack BD. Degradation is considered in terms of the pronounced localized leakage contribution through the high–κ and interlayer SiOx. Simultaneous nanoscale current–voltage (I-V) characteristics and C–AFM imaging illlutrates charge trapping/decay from the native or stress induced traps with intrinsic charge lateral propagation. A post–stress/BD constant voltage imaging shows effects of stress bias polarity on the BD induced topography and trap assisted nano–current variations. Physical attributes of deformed artifacts relate strongly to the polarity of electron injection (gate or substrate) so discriminating the trap generation in high–κ and interlayer SiOx revealing non–homogeneous (dynamic) nature of leakage.

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Fault Isolation of MOL and FEOL Buried Defects Using Conductive Atomic Force Microscopy as a Complement to Passive Voltage Contrast Imaging

ISTFA 2017: Conference Proceedings from the 43rd International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2017p0606 ◽

2017 ◽

Author(s):

Lucile C. Teague Sheridan ◽

Linda Conohan ◽

Chong Khiam Oh

Keyword(s):

Atomic Force Microscopy ◽

Cmos Technology ◽

Fault Isolation ◽

Contrast Imaging ◽

Conductive Atomic Force Microscopy ◽

Isolation Technique ◽

Conductive Afm ◽

Force Microscopy ◽

Atomic Force ◽

Voltage Contrast

Abstract Atomic force microscopy (AFM) methods have provided a wealth of knowledge into the topographic, electrical, mechanical, magnetic, and electrochemical properties of surfaces and materials at the micro- and nanoscale over the last several decades. More specifically, the application of conductive AFM (CAFM) techniques for failure analysis can provide a simultaneous view of the conductivity and topographic properties of the patterned features. As CMOS technology progresses to smaller and smaller devices, the benefits of CAFM techniques have become apparent [1-3]. Herein, we review several cases in which CAFM has been utilized as a fault-isolation technique to detect middle of line (MOL) and front end of line (FEOL) buried defects in 20nm technologies and beyond.

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Fault Localization in Contact Level by Using Conductive Atomic Force Microscopy

ISTFA 2003: Conference Proceedings from the 29th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2003p0413 ◽

2003 ◽

Author(s):

Jon C. Lee ◽

J. H. Chuang

Keyword(s):

Atomic Force Microscopy ◽

Integrated Circuits ◽

Fault Localization ◽

Electrical Characterization ◽

Conductive Atomic Force Microscopy ◽

Force Microscopy ◽

Atomic Force ◽

Optical Electron ◽

Defect Isolation ◽

Voltage Contrast

Abstract As integrated circuits (IC) have become more complicated with device features shrinking into the deep sub-micron range, so the challenge of defect isolation has become more difficult. Many failure analysis (FA) techniques using optical/electron beam and scanning probe microscopy (SPM) have been developed to improve the capability of defect isolation. SPM provides topographic imaging coupled with a variety of material characterization information such as thermal, magnetic, electric, capacitance, resistance and current with nano-meter scale resolution. Conductive atomic force microscopy (C-AFM) has been widely used for electrical characterization of dielectric film and gate oxide integrity (GOI). In this work, C-AFM has been successfully employed to isolate defects in the contact level and to discriminate various contact types. The current mapping of C-AFM has the potential to identify micro-leaky contacts better than voltage contrast (VC) imaging in SEM. It also provides I/V information that is helpful to diagnose the failure mechanism by comparing I/V curves of different contact types. C-AFM is able to localize faulty contacts with pico-amp current range and to characterize failure with nano-meter scale lateral resolution. C-AFM should become an important technique for IC fault localization. FA examples of this technique will be discussed in the article.

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