scholarly journals Selection of the two enantiotropic polymorphs of diF-TES-ADT in solution sheared thin film transistors

2020 ◽  
Vol 8 (43) ◽  
pp. 15361-15367
Author(s):  
Tommaso Salzillo ◽  
Nieves Montes ◽  
Raphael Pfattner ◽  
Marta Mas-Torrent

The modulation of the deposition speed in blends of diF-TES-ADT and polystyrene controls the formation of either the low-temperature or the high-temperature polymorph.

2019 ◽  
Vol 10 ◽  
pp. 1125-1130 ◽  
Author(s):  
Dapeng Wang ◽  
Mamoru Furuta

This study examines the effect of the annealing temperature on the initial electrical characteristics and photo-induced instabilities of amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs). The extracted electrical parameters from transfer curves suggest that a low-temperature treatment maintains a high density of defects in the IGZO bulk, whereas high-temperature annealing causes a quality degradation of the adjacent interfaces. Light of short wavelengths below 460 nm induces defect generation in the forward measurement and the leakage current increases in the reverse measurement, especially for the low-temperature-annealed device. The hysteresis after negative-bias-illumination-stress (NBIS) is quantitatively investigated by using the double-scan mode and a positive gate pulse. Despite the abnormal transfer properties in the low-temperature-treated device, the excited holes are identically trapped at the front interface irrespective of treatment temperature. NBIS-induced critical instability occurs in the high-temperature-annealed TFT.


2021 ◽  
Vol 723 ◽  
pp. 138594
Author(s):  
Qian Zhang ◽  
Cheng Ruan ◽  
Guodong Xia ◽  
Hongyu Gong ◽  
Sumei Wang

2014 ◽  
Vol 55 ◽  
pp. 99-105 ◽  
Author(s):  
Joohye Jung ◽  
Si Joon Kim ◽  
Keun Woo Lee ◽  
Doo Hyun Yoon ◽  
Yeong-gyu Kim ◽  
...  

2011 ◽  
Vol 1287 ◽  
Author(s):  
Anupama Mallikarjunan ◽  
Laura M Matz ◽  
Andrew D Johnson ◽  
Raymond N Vrtis ◽  
Manchao Xiao ◽  
...  

ABSTRACTThe electrical and physical quality of gate and passivation dielectrics significantly impacts the device performance of thin film transistors (TFTs). The passivation dielectric also needs to act as a barrier to protect the TFT device. As low temperature TFT processing becomes a requirement for novel applications and plastic substrates, there is a need for materials innovation that enables high quality plasma enhanced chemical vapor deposition (PECVD) gate dielectric deposition. In this context, this paper discusses structure-property relationships and strategies for precursor development in silicon nitride, silicon oxycarbide (SiOC) and silicon oxide films. Experiments with passivation SiOC films demonstrate the benefit of a superior precursor (LkB-500) and standard process optimization to enable lower temperature depositions. For gate SiO2 deposition (that are used with polysilicon TFTs for example), organosilicon precursors containing different types and amounts of Si, C, O and H bonding were experimentally compared to the industry standard TEOS (tetraethoxysilane) at different process conditions and temperatures. Major differences were identified in film quality especially wet etch rate or WER (correlating to film density) and dielectric constant (k) values (correlating to moisture absorption). Gate quality SiO2 films can be deposited by choosing precursors that can minimize residual Si-OH groups and enable higher density stable moisture-free films. For e.g., the optimized precursor AP-LTO® 770 is clearly better than TEOS for low temperature PECVD depositions based on density, WER, k charge density (measured by flatband voltage or Vfb); and leakage and breakdown voltage (Vbd) measurements. The design and development of such novel precursors is a key factor to successfully enable manufacturing of advanced low temperature processed devices.


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