Modelling and behavioural simulation of a high-speed phase-locked loop for frequency synthesis

2012 ◽  
Vol 6 (3) ◽  
pp. 195 ◽  
Author(s):  
K. Kalita ◽  
J. Handique ◽  
T. Bezboruah
2018 ◽  
Vol 66 (12) ◽  
pp. 5922-5932 ◽  
Author(s):  
Farshid Ashtiani ◽  
Pouria Sanjari ◽  
Mohamad Hossein Idjadi ◽  
Firooz Aflatouni

2018 ◽  
Vol 7 (3.12) ◽  
pp. 871
Author(s):  
Thejusraj. H ◽  
Prithivi Raj ◽  
J Selvakumar ◽  
S Praveen Kumar

This paper presents the analysis of various oscillators that generate high frequency of oscillation for high speed communication, clock generation and clock recovery. The Ring oscillator and the Current Starved Voltage Controlled Oscillator(CSVCO) (for 5-stagewithout resistor and with resistor) have been implemented using the Cadence Virtuoso tool in 90 nm technology. The generated frequency of oscillation and the power consumption values of the voltage controlled oscillators have been calculated after inclusion in the PLL, and were also compared to identify the most suitable voltage controlled oscillator for a given application.


2011 ◽  
Vol 80-81 ◽  
pp. 1249-1257
Author(s):  
Bang Cheng Han ◽  
Dan He ◽  
Fang Zheng Guo ◽  
Yu Wang ◽  
Bing Nan Huang

A phase-locked loop (PLL) control system based on field programmable gates array (FPGA) is proposed through analyzing the model of three-phase unipolar-driven BLDCM (brushless direct current motor) to enhance the reliability and accurate steady-state speed for magnetically suspended control moment gyroscope (MSCMG). The numerical operation module, PLL module and current-loop control module are designed based on FPGA using very-high-speed integrated circuit hardware description language (VHDL) to realize the control law of the digital system. The pulse width modulation (PWM) generating module for Buck converter, the commutation signal generating module for the inverter and ADC module are designed for driving the motor and sampling the current signal. The PLL is analyzed and optimized in the paper and all the modules are verified using the software of ModelSim and the experiments. The simulation and experiment results on BLDCM of MSCMG show that the stability of the motor velocity can reach 0.01% and 0.02% respectively by the PLL technology based on FPGA, which is difficult to be obtained by conventional proportion integral different (PID) speed control.


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