Correlation between midgap interface state density and thickness‐averaged oxide stress and strain at Si/SiO2interfaces formed by thermal oxidation of Si

1990 ◽  
Vol 56 (20) ◽  
pp. 1983-1985 ◽  
Author(s):  
C. H. Bjorkman ◽  
J. T. Fitch ◽  
G. Lucovsky
Keyword(s):  
Thermal Oxidation ◽  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Stress And Strain ◽  
Oxide Stress

High Channel Mobility in P-Channel MOSFETs Fabricated on 4H-SiC (0001) and Non-Basal Faces

2009 ◽  
Vol 615-617 ◽  
pp. 789-792
Author(s):  
Masato Noborio ◽  
Jun Suda ◽  
Tsunenobu Kimoto
Keyword(s):  
Thermal Oxidation ◽  
Interface State ◽  
Original Method ◽  
State Density ◽  
Interface State Density ◽  
Gate Oxides ◽  
Channel Mobility ◽  
Mos Devices

P-channel MOSFETs have been fabricated on 4H-SiC (0001) face as well as on 4H-SiC (03-38) and (11-20) faces. The gate oxides were formed by thermal oxidation in dry N2O ambient, which is widely accepted to improve the performance of n-channel SiC MOSFETs. The p-channel SiC MOSFETs with N2O-grown oxides on 4H-SiC (0001), (03-38), and (11-20) faces show a channel mobility of 7 cm2/Vs, 11 cm2/Vs, and 17 cm2/Vs, respectively. From the quasi-static C-V curves measured by using gate-controlled diodes, the interface state density was calculated by an original method. The interface state density was the lowest at the SiO2/4H-SiC (03-38) interface (about 1x1012 cm-2eV-1 at EV + 0.2 eV). The authors have applied deposited oxides to the 4H-SiC p-channel MOSFETs. The (0001), (03-38), and (11-20) MOSFETs with deposited oxides exhibit a channel mobility of 10 cm2/Vs, 13 cm2/Vs, and 17 cm2/Vs, respectively. The deposited oxides are one of effective approaches to improve both n-channel and p-channel 4H-SiC MOS devices.

Characteristics of Thin Layers of SiO2 Fabricated by Rapid Thermal Oxidation

1987 ◽  
Vol 92 ◽  
Author(s):  
S. Prasad ◽  
J. Haase ◽  
R. Früchtnicht ◽  
R. Ferretti ◽  
D. Haack
Keyword(s):  
Growth Rate ◽  
Thermal Oxidation ◽  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Thin Layers ◽  
Rapid Thermal Oxidation ◽  
High Temperature Anneal ◽  
Work Function Difference ◽  
Function Difference

ABSTRACTThin layers of SiO2 (60-300 Å) were fabricated by rapid thermal oxidation (RTO). Growth rate on (100) and (111) Si was determined. Two different high-temperature anneal cycles were used to reduce the interface state density. Work function difference between metal and semiconductor depends upon technology and can be attributed to the changes in Si-SiO2 barrier height.

Interface-State-Density Evaluation of p-type and n-type Ge/GeNx Structures by Conductance Technique

2013 ◽  
Vol 133 (7) ◽  
pp. 1279-1284
Author(s):  
Takuro Iwasaki ◽  
Toshiro Ono ◽  
Yohei Otani ◽  
Yukio Fukuda ◽  
Hiroshi Okamoto
Keyword(s):  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Conductance Technique ◽  
Density Evaluation ◽  
P Type

Identification of Charging Effects in Plasma-Enhanced TEOS Deposition with Non-Contact Test Techniques

1998 ◽  
Author(s):  
Tomasz Brozek ◽  
James Heddleson
Keyword(s):  
Vapor Deposition ◽  
Chemical Vapor ◽  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Wafer Surface ◽  
Oxide Charge ◽  
Contact Test ◽  
Deposition Power ◽  
Oxide Deposition

Abstract Use of non-contact test techniques to characterize degradation of the Si-SiO2 system on the wafer surface exposed to a plasma environment have proven themselves to be sensitive and useful in investigation of plasma charging level and uniformity. The current paper describes application of the surface charge analyzer and surface photo-voltage tool to explore process-induced charging occurring during plasma enhanced chemical vapor deposition (PECVD) of TEOS oxide. The oxide charge, the interface state density, and dopant deactivation are studied on blanket oxidized wafers with respect to the effect of oxide deposition, power lift step, and subsequent annealing.

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