Dry etch damage in inductively coupled plasma exposed GaAs/AlGaAs heterojunction bipolar transistors

ABSTRACTLow resistance ohmic contacts are difficult to form to p-type GaN and AlGaN due to the unavailability of growth methods for highly p-doped GaN and AlGaN. A p-type carbon-doped GaAs regrowth on p-GaN prior to ohmic metallization has been shown in previous work to improve contact resistance to p-GaN [13]. Applying the regrowth method to the p-base regions of npn structured bipolar transistors, AlGaN/GaN heterojunction bipolar transistors and GaN bipolar junction transistors have been demonstrated. GaN/AlGaN epilayers were grown with a molecular beam epitaxy system. Highly carbon-doped p-GaAs (1020 cm−3) was regrown on the devices (∼500 Å) in the base contact region by metal organic chemical vapor deposition after emitter mesa etching. Emitter and base mesa structures were formed by Inductively Coupled Plasma etching under low damage conditions with a Cl2/Ar chemistry. SiO2 was used for emitter sidewall formation to reduce leakage current to the emitter, as well as for a mask for GaAs base regrowth. Very high current densities were obtained for common base operation in both device types. The devices were operable at 250 °C.

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Sidewall Slope Control of InP Via Holes for 3D Integration

Micromachines ◽

10.3390/mi12010089 ◽

2021 ◽

Vol 12 (1) ◽

pp. 89

Author(s):

Jongwon Lee ◽

Kilsun Roh ◽

Sung-Kyu Lim ◽

Youngsu Kim

Keyword(s):

Inductively Coupled Plasma ◽

Sio2 Layer ◽

Etch Depth ◽

Rf Power ◽

3D Integration ◽

Inductively Coupled ◽

Wide Range ◽

Via Holes ◽

Dry Etch ◽

Icp Etcher

This is the first demonstration of sidewall slope control of InP via holes with an etch depth of more than 10 μm for 3D integration. The process for the InP via holes utilizes a common SiO2 layer as an InP etch mask and conventional inductively coupled plasma (ICP) etcher operated at room temperature and simple gas mixtures of Cl2/Ar for InP dry etch. Sidewall slope of InP via holes is controlled within the range of 80 to 90 degrees by changing the ICP power in the ICP etcher and adopting a dry-etched SiO2 layer with a sidewall slope of 70 degrees. Furthermore, the sidewall slope control of the InP via holes in a wide range of 36 to 69 degrees is possible by changing the RF power in the etcher and introducing a wet-etched SiO2 layer with a small sidewall slope of 2 degrees; this wide slope control is due to the change of InP-to-SiO2 selectivity with RF power.

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Hydrogenation and Defect Creation in GaAs-Based Devices During High Density Plasma Processing

MRS Proceedings ◽

10.1557/proc-510-209 ◽

1998 ◽

Vol 510 ◽

Cited By ~ 1

Author(s):

T. Maeda ◽

J. W. Lee ◽

C. R. Abernathy ◽

S. J. Pearton ◽

F. Ren ◽

...

Keyword(s):

Heterojunction Bipolar Transistors ◽

Inductively Coupled Plasma ◽

Electron Cyclotron Resonance ◽

Field Effect Transistors ◽

High Electron Mobility Transistors ◽

High Electron ◽

Source Power ◽

Ion Energy ◽

Inductively Coupled ◽

Self Bias

AbstractThe effects of Inductively Coupled Plasma (ICP) and Electron Cyclotron Resonance (ECR) H2 plasmas on GaAs metal semiconductor field effect transistors (MESFETs), high electron mobility transistors (HEMTs) and heterojunction bipolar transistors (HBTs) have been measured as a function of ion flux, ion energy and process pressure. The chemical effects of hydrogenation have been compared to direct physical bombardment by Ar plasmas under the same conditions. Si dopant passivation in MESFETs and HEMTs and C base-dopant passivation in HBTs produces much larger changes in sheet resistance, breakdown voltage and device gain or transconductance than Ar ion bombardment and suggests that H2-containing plasma chemistries (CH4/H2 for semiconductor etching, SiH4 for dielectric deposition, CHF3 for dielectric etching) should be avoided, or at least the exposure of the surface minimized. In some cases the device degradation is less for higher source power conditions, due to the suppression of cathode dc self-bias and hence ion energy.

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Post Annealing Etch Process for Improved Reverse Characteristics of 4H-SiC Diode

Materials Science Forum ◽

10.4028/www.scientific.net/msf.615-617.663 ◽

2009 ◽

Vol 615-617 ◽

pp. 663-666

Author(s):

In Ho Kang ◽

Wook Bahng ◽

Sung Jae Joo ◽

Sang Cheol Kim ◽

Nam Kyun Kim

Keyword(s):

Inductively Coupled Plasma ◽

Schottky Diodes ◽

Annealing Process ◽

Activation Process ◽

Electrical Characteristics ◽

Inductively Coupled ◽

Edge Termination ◽

Post Annealing ◽

Surface Damages ◽

Dry Etch

The effects of post annealing etch process on electrical performances of a 4H-SiC Schottky diodes without any edge termination were investigated. The post etch was carried out using various dry the dry etch techniques such as Inductively Coupled Plasma (ICP) and Neutral Beam Etch (NBE) in order to eliminate suspicious surface damages occurring during a high temperature ion activation process. The leakage current of diodes treated by NBE measured at -100V was about one order lower than that of diode without post etch and a half times lower than that of diode treated by ICP without a significant degradation of forward electrical characteristics. Based on the above results, the post annealing process was adapted to a junction barrier Schottky diode with a field limiting ring. The blocking voltages of diode without post annealing etch and diodes treated by ICP and NBE were -1038V, -1125V, and -1595V, respectively.

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Improvement of III-N Surfaces After Inductively Coupled Plasma Dry Etch Exposure

ECS Meeting Abstracts ◽

10.1149/ma2005-01/13/595 ◽

2005 ◽

Keyword(s):

Inductively Coupled Plasma ◽

Inductively Coupled ◽

Dry Etch

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Investigating GaSb(001) Dry Etching by ICP-RIE on a non-Silicon Containing Sample Holder with no Organic Gases

MRS Proceedings ◽

10.1557/opl.2012.775 ◽

2012 ◽

Vol 1396 ◽

Author(s):

Hamad A. Albrithen ◽

Gale S. Petrich ◽

Leslie A. Kolodziejski ◽

Abdelmajid Salhi ◽

Abdulrahman A. Almuhanna

Keyword(s):

Inductively Coupled Plasma ◽

Silicon Oxide ◽

Etching Rate ◽

Sample Holder ◽

Inductively Coupled ◽

Solid Films ◽

Mask Layer ◽

Organic Gases ◽

Dry Etch ◽

Anisotropic Etch

ABSTRACTWe report the dry etch of GaSb(001) by inductively coupled plasma reactive ion etcher. Silicon Oxide, deposited by PECVD, was used as a mask. The oxide layer proved to be almost unaffected compared to the GaSb, when using chlorine compound gases as etchants (Cl2, BCl3, and SiCl4) as well as argon. This provides high selectivity for GaSb to the mask layer. The sample holder has no silicon that may contribute to the etching process. Etching using Cl2 + Ar showed increase in the etching rate as the chlorine ratio increases; however, the process led to grassy surface and chemical like reaction. The use of SiCl4+Cl2+Ar mixture with low chlorine ratio resulted in anisotropic etch with smooth sides. It has been found for this case that the increase of the chlorine ratio led to an increased etching rate as well. The repeat of previously reported result by Swaminathan et al. [Thin Solid Films 516 (2008) 8712.] yet with a sample holder not having silicon, proved the effect of Si-contribution in producing vertical profile etch with smooth surfaces.

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Comparison of dry etch damage in GaAs/AlGaAs heterojunction bipolar transistors exposed to ECR and ICP Ar plasmas

Solid-State Electronics ◽

10.1016/s0038-1101(97)00247-5 ◽

1998 ◽

Vol 42 (5) ◽

pp. 733-742 ◽

Cited By ~ 6

Author(s):

J.W Lee ◽

C.R Abernathy ◽

S.J Pearton ◽

F Ren ◽

C Constantine ◽

...

Keyword(s):

Heterojunction Bipolar Transistors ◽

Bipolar Transistors ◽

Dry Etch

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High yield scalable dry etch process for indium based heterojunction bipolar transistors

LEOS 1992 Summer Topical Meeting Digest on Broadband Analog and Digital Optoelectronics, Optical Multiple Access Networks, Integrated Optoelectronics, and Smart Pixels ◽

10.1109/iciprm.1992.235682 ◽

2003 ◽

Author(s):

T.R. Fullowan ◽

S.J. Pearton ◽

R.F. Kopf ◽

F. Ren ◽

J. Lothian

Keyword(s):

Heterojunction Bipolar Transistors ◽

Bipolar Transistors ◽

High Yield ◽

Dry Etch

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ICP (inductively coupled plasma) dry etch of DUV MoSi HTPSM

10.1117/12.360204 ◽

1999 ◽

Cited By ~ 1

Author(s):

Kyu-Yong Lee ◽

Lee-Ju Kim ◽

Kyung-Han Nam ◽

Keuntaek Park ◽

Y. M. Ku ◽

...

Keyword(s):

Inductively Coupled Plasma ◽

Inductively Coupled ◽

Dry Etch

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Dry Etch Self-Aligned AlInAs/InGaAs Heterojunction Bipolar Transistors

MRS Proceedings ◽

10.1557/proc-240-285 ◽

1991 ◽

Vol 240 ◽

Author(s):

T. R. Fullowan ◽

S. J. Pearton ◽

R. F. Kopf ◽

F. Ren ◽

Y. K. Chen ◽

...

Keyword(s):

Plasma Etching ◽

Heterojunction Bipolar Transistors ◽

High Speed ◽

Large Scale ◽

Electron Cyclotron Resonance ◽

Layer Structure ◽

Digital Circuit ◽

Bipolar Transistors ◽

High Yield ◽

Dry Etch

ABSTRACTA dry etch fabrication technology for high-speed AlInAs/InGaAs Heterojunction Bipolar Transistors (HBT's) utilizing low-damage Electron Cyclotron Resonance (ECR) CH4/H2/Ar plasma etching is detailed. The dry etch process uses triple self-alignment of the emitter and base metals and the base mesa, minimizing the base-collector capacitance (CBC). Devices with 2 × 4 μm2 emitters demonstrated current gains of 30–50 with ft and fmax values of ≥ 80 GHz and ≥100 GHz respectively. The structure employs a two-stage collector to achieve breakdown voltage (Vceo ) of 7V. The combination of processing and layer structure delivers truly scalable high yield AlInAs/InGaAs HBT's with both DC and RF characteristics suitable for large-scale, high speed digital circuit applications.

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