High frequency capacitance-voltage technique for the extraction of interface trap density of the heterojunction capacitor: Terman’s method revised

The interface and bulk trap densities were separately extracted from self-aligned top-gate (SA-TG) coplanar indium gallium zinc oxide (IGZO) thin-film transistors (TFTs) using the low-frequency capacitance–voltage (C–V) characteristics and space-charge-limited current (SCLC) under the flat-band condition. In the method based on the C–V curve, the energy distribution of the interface trap density was extracted using the low-frequency C–V characteristics, and that of the bulk trap density was obtained by subtracting the density of interface trap states from the total subgap density of states (DOS) at each energy level. In the SCLC-based method, the energy distribution of the bulk trap density was extracted using the SCLC under the flat-band condition at high drain-to-source voltages, and that of the interface trap density was obtained by subtracting the density of bulk trap components from the total subgap DOS at each energy level. In our experiments, the two characterization techniques provided very similar interface and bulk trap densities and showed that approximately 60% of the subgap states originate from the IGZO/SiO2 interface at the conduction band edge in the fabricated IGZO TFTs, although the two characterization techniques are based on different measurement data. The results of this study confirm the validity of the characterization techniques proposed to separately extract the interface and bulk trap densities in IGZO TFTs. Furthermore, these results show that it is important to reduce the density of interface trap states to improve the electrical performance and stability of fabricated SA-TG coplanar IGZO TFTs.

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Lateral Non-Uniformity Charges Influence on Interface Trap Density (Dit) by Terman Method in the nMOS Fabrication

Advanced Materials Research ◽

10.4028/www.scientific.net/amr.690-693.1846 ◽

2013 ◽

Vol 690-693 ◽

pp. 1846-1850

Author(s):

Shen Li Chen ◽

Yet Fan Chang

Keyword(s):

Oxide Layer ◽

High Frequency ◽

Frequency Measurement ◽

Trap Density ◽

Interface Trap Density ◽

Interface Trap ◽

Oxide Interface ◽

Interface Quality ◽

Thin Oxide

Generally speaking, the oxide interface quality can be determined by the interface trap density (Dit) distribution. In this paper, the Dit quantity obtained from the Terman method, which it is assumed that the Dit is equal to zero at the beginning for simulating the Dit effect in ultra-thin oxide. However, the lateral non-uniformity charges have existed in the oxide layer, which maybe obtained an equivalent Dit density not equal to zero also producing an equivalent Dit value. And, such faked Dit will be resulted in an error in high frequency measurement. Fortunately, it can be solved by differentiating technique to obtain an accuracy Dit quantity.

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GaN MOS Structures with Low Interface Trap Density

Solid State Phenomena ◽

10.4028/www.scientific.net/ssp.314.79 ◽

2021 ◽

Vol 314 ◽

pp. 79-83

Author(s):

Rong Ming Chu

Keyword(s):

High Frequency ◽

Electronic Devices ◽

Surface Preparation ◽

Trap Density ◽

Interface Trap Density ◽

Interface Trap ◽

Device Performance ◽

Great Success ◽

New Device ◽

Mos Structures

GaN based electronic devices have gained great success in the arena of high-frequency and high-power applications. A high-quality GaN MOS structure has the potential to enable new device designs and higher device performance, thereby bringing the success of GaN electronics to a new level. This paper discusses results of the work on GaN MOS structures show that with adequate surface preparation samples featuring interface trap density down to the ~ 1010 eV-1cm-2 range can be formed.

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Extraction of Average Interface Trap Density using Capacitance-Voltage Characteristic at SiGe p-FinFET and Verification using Terman's Method

Journal of the Institute of Electronics and Information Engineers ◽

10.5573/ieie.2015.52.4.056 ◽

2015 ◽

Vol 52 (4) ◽

pp. 56-61

Author(s):

Hyunsoo Kim ◽

Youngsoo Seo ◽

Hyungcheol Shin

Keyword(s):

Voltage Characteristic ◽

Trap Density ◽

Interface Trap Density ◽

Interface Trap ◽

Capacitance Voltage

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Comparison of the Electrical Properties of Thermal and Ion Beam Oxides

MRS Proceedings ◽

10.1557/proc-93-137 ◽

1987 ◽

Vol 93 ◽

Author(s):

David J. Dumin ◽

E. R. Fossum ◽

S. S. Todorov

Keyword(s):

Silicon Oxide ◽

Ion Beam ◽

Trap Density ◽

Interface Trap Density ◽

Interface Trap ◽

Charge Densities ◽

Interface Charge ◽

Current Voltage ◽

Capacitance Voltage ◽

Order Of Magnitude

ABSTRACTA comparison of the current-voltage (I-V) and the capacitance-voltage (C-V) characteristics of thermal and low temperature ion beam grown films of silicon oxide was made. The oxides were in the thickness range between 5 nm and 10 nm. The ion beam oxides were grown at room temperature. The bulk resistivities of the thermal oxides were about 1017 ohm cm and were about 5 orders of magnitude lower for the ion beam oxides. The interface charge densities at the Si-SiO2 interface were about an order of magnitude higher in the case of the ion beam oxides. The oxide properties were also measured after current stressing at constant voltages. The thermal oxides showed an increase in the interface trap density at the Si-SiO2 interface after stressing with a distinct trap appearing above mid-gap. The ion beam oxides showed very little increase in the interface trap density after stressing. The higher conductivity of the ion beam oxides may have lead to discharging of the interface traps generated during stressing.

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