Lateral Non-Uniformity Charges Influence on Interface Trap Density (Dit) by Terman Method in the nMOS Fabrication

2013 ◽  
Vol 690-693 ◽  
pp. 1846-1850
Author(s):  
Shen Li Chen ◽  
Yet Fan Chang

Generally speaking, the oxide interface quality can be determined by the interface trap density (Dit) distribution. In this paper, the Dit quantity obtained from the Terman method, which it is assumed that the Dit is equal to zero at the beginning for simulating the Dit effect in ultra-thin oxide. However, the lateral non-uniformity charges have existed in the oxide layer, which maybe obtained an equivalent Dit density not equal to zero also producing an equivalent Dit value. And, such faked Dit will be resulted in an error in high frequency measurement. Fortunately, it can be solved by differentiating technique to obtain an accuracy Dit quantity.

2017 ◽  
Vol 178 ◽  
pp. 145-149 ◽  
Author(s):  
A. Gaur ◽  
Y. Balaji ◽  
D. Lin ◽  
C. Adelmann ◽  
J. Van Houdt ◽  
...  

2016 ◽  
Vol 858 ◽  
pp. 647-650
Author(s):  
Zhao Yang Peng ◽  
Yi Yu Wang ◽  
Hua Jun Shen ◽  
Yun Bai ◽  
Yi Dan Tang ◽  
...  

Effects of NO and forming gas annealing treatment on the interface quality and reliability of 4H-SiC MOS were systematically studied by low temperature conductance measurements in combination with time-zero dielectric breakdown and time-dependent dielectric breakdown methods. The interface trap density (Dit) showed no obvious reduction after forming gas annealing, and the values of Dit decreased significantly after combined NO and forming gas annealing treatment. The F-N barrier height, electric field to breakdown (Ebd) and charge to breakdown (Qbd) of the MOS structure increased from 2.42 eV, 10 MV/cm, 1mC/cm2 to 2.62 eV, 10.7 MV/cm, 78mC/cm2 after forming gas annealing. The values of F-N barrier height, Ebd and Qbd for MOS capacitors with combined NO and forming gas annealing treatment are 2.69 eV, 10.2 MV/cm, and 24mC/cm2. These results suggest that forming gas annealing is more effective in reliability improvement. While when considering the interface trap density, it seems that combined NO and forming gas annealing treatment is a better choice.


2021 ◽  
Vol 314 ◽  
pp. 79-83
Author(s):  
Rong Ming Chu

GaN based electronic devices have gained great success in the arena of high-frequency and high-power applications. A high-quality GaN MOS structure has the potential to enable new device designs and higher device performance, thereby bringing the success of GaN electronics to a new level. This paper discusses results of the work on GaN MOS structures show that with adequate surface preparation samples featuring interface trap density down to the ~ 1010 eV-1cm-2 range can be formed.


2020 ◽  
Vol 13 (11) ◽  
pp. 111006
Author(s):  
Li-Chuan Sun ◽  
Chih-Yang Lin ◽  
Po-Hsun Chen ◽  
Tsung-Ming Tsai ◽  
Kuan-Ju Zhou ◽  
...  

2007 ◽  
Vol 28 (3) ◽  
pp. 232-234 ◽  
Author(s):  
G. Kapila ◽  
B. Kaczer ◽  
A. Nackaerts ◽  
N. Collaert ◽  
G. V. Groeseneken

2008 ◽  
Vol 55 (2) ◽  
pp. 547-556 ◽  
Author(s):  
Koen Martens ◽  
Chi On Chui ◽  
Guy Brammertz ◽  
Brice De Jaeger ◽  
Duygu Kuzum ◽  
...  

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