Field-effect trap-level-distribution model of dynamic random access memory data retention characteristics

1997 ◽  
Vol 81 (10) ◽  
pp. 7053-7060 ◽  
Author(s):  
A. Hiraiwa ◽  
M. Ogasawara ◽  
N. Natsuaki ◽  
Y. Itoh ◽  
H. Iwai
1996 ◽  
Vol 80 (5) ◽  
pp. 3091-3099 ◽  
Author(s):  
A. Hiraiwa ◽  
M. Ogasawara ◽  
N. Natsuaki ◽  
Y. Itoh ◽  
H. Iwai

1997 ◽  
Author(s):  
Atsushi Hiraiwa ◽  
Makoto Ogasawara ◽  
Nobuyoshi Natsuaki ◽  
Yutaka Itoh ◽  
Hidetoshi Iwai

2020 ◽  
Vol 1 ◽  
pp. 163-169
Author(s):  
Hyangwoo Kim ◽  
Hyeonsu Cho ◽  
Byoung Don Kong ◽  
Jin-Woo Kim ◽  
Meyya Meyyappan ◽  
...  

2021 ◽  
Author(s):  
Hyangwoo Kim ◽  
Hyeonsu Cho ◽  
Hyeon-Tak Kwak ◽  
Myunghae Seo ◽  
Seungho Lee ◽  
...  

Abstract Three-terminal (3-T) thyristor random-access memory is explored for a next generation high-density nanoscale vertical cross-point array. The effects of standby voltages on the device are thoroughly investigated in terms of gate-cathode voltage (VGC,ST) and anode- cathode voltage (VAC,ST) in the standby state for superior data retention characteristics and low-power operation. The device with the optimized VGC,ST of -0.4 V and VAC,ST of 0.6 V shows the continuous data retention capability without refresh operation with a low standby current of 1.14 pA. In addition, a memory array operation scheme of 3-T TRAM is proposed to address array disturbance issues. The presented array operation scheme can efficiently minimize program, erase and read disturbances on unselected cells by adjusting gate-cathode voltage. The standby voltage turns out to be beneficial to improve retention characteristics: over 10 s. With the proposed memory array operation, 3-T TRAM can provide excellent data retention characteristics and high-density memory configurations comparable with or surpass conventional dynamic random-access memory (DRAM) technology.


Nanomaterials ◽  
2020 ◽  
Vol 10 (3) ◽  
pp. 457 ◽  
Author(s):  
Lei Wu ◽  
Hongxia Liu ◽  
Jinfu Lin ◽  
Shulong Wang

A self-compliance resistive random access memory (RRAM) achieved through thermal annealing of a Pt/HfOx/Ti structure. The electrical characteristic measurements show that the forming voltage of the device annealing at 500 °C decreased, and the switching ratio and uniformity improved. Tests on the device’s cycling endurance and data retention characteristics found that the device had over 1000 erase/write endurance and over 105 s of lifetime (85 °C). The switching mechanisms of the devices before and after annealing were also discussed.


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