Determination of hot-carrier induced interface state density in polycrystalline silicon thin-film transistors

1998 ◽  
Vol 84 (4) ◽  
pp. 2341-2348 ◽  
Author(s):  
L. Mariucci ◽  
G. Fortunato ◽  
R. Carluccio ◽  
A. Pecora ◽  
S. Giovannini ◽  
...  
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Polycrystalline Silicon ◽  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Silicon Thin Film ◽  
Hot Carrier

Investigation of the off-current in amorphous silicon thin film transistors for SiO2 and SiNx. gate insulators

1996 ◽  
Vol 424 ◽  
Author(s):  
Jeong Hyun Kim ◽  
Woong Sik Choi ◽  
Chan Hee Hong ◽  
Hoe Sup Soh
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Thin Film Transistors ◽  
Chemical Vapor ◽  
Interface State ◽  
State Density ◽  
Gate Insulator ◽  
Defect States ◽  
Silicon Thin Film ◽  
Pressure Chemical

AbstractThe off current behavior of hydrogenated amorphous silicon (a-Si:H) thin film transistors (TFTs) with an atmospheric pressure chemical vapor deposition (APCVD) silicon dioxide (SiO2) gate insulator were investigated at negative gate voltages. The a-Si:H TFT with SiO2 gate insulator has small off currents and large activation energy (Ea) of the off current compared to the a-Si:H TFT with SiNx gate insulator. The holes induced in the channel by negative gate voltage seem to be trapped in the defect states near the a-Si:H/SiO2 interface. The interface state density in the lower half of the band gap of a-Si:H/SiO2 appears to be much higher than that for a-Si:H/SiNx.

EFFECT OF TRAP STATES AT THE OXIDE-SILICON INTERFACE IN POLYCRYSTALLINE SILICON THIN-FILM TRANSISTORS

2008 ◽  
Vol 22 (30) ◽  
pp. 5357-5364
Author(s):  
NAVNEET GUPTA
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Polycrystalline Silicon ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
State Density ◽  
Trap States ◽  
Silicon Thin Film ◽  
Gate Oxide Thickness ◽  
Silicon Interface

This work presents the study of the effect of trap states at the oxide-silicon interface in lightly doped polycrystalline silicon thin-film transistors with large grains. In this study, it is assumed that the oxide-silicon interface traps are evenly distributed throughout the interface region and single grain boundary is present in the channel of poly-Si TFT. It is shown that improved device characteristics can be obtained by reducing the gate oxide thickness. It is also observed that as gate oxide thickness decreases for a constant value of trap state density in the oxide-silicon interface, the gate voltage required for channel formation is lowered and leads to a decrease in threshold voltage of the device. Calculated and experimental results are also found to be well consistent with each other.

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