C-axis oriented growth of ZnO nanorods over Mg:GaN for improved heterojunction device performance

Heterojunction diode based on n-ZnO nanorods/p-Silicon (Si) assembly was fabricated, examined and reported here. Horizontal quartz tube thermal evaporation technique was used for the growth of ZnO nanorods on Si substrate. The nanorods were characterized by several techniques to examine the structural, morphological, scattering and electrical properties. Wurtzite hexagonal phase of the grown aligned nanorods was observed using X-ray diffraction (XRD) and scanning electron microscopy (SEM). The appearance of a sharp Raman peak at 438 cm–1 was observed and it is related to the E2(high) mode of the wurtzite hexagonal phase of ZnO. The electrical properties of the fabricated heterojunction assembly were examined at different temperatures (298∼398 K) in both reverse and forward biased conditions, and a good stability was observed over the entire temperature range. A reduction in the turn-on and breakdown voltage was observed with increasing temperature. By increasing the temperature, the effective potential barrier height was increased, while quality factor was decreased. The observed activation energy was found to be ∼93.4 meV, higher than the exciton binding energy of ZnO.

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Synthesis and Controlled Growth of ZnO Nanorods Based Hybrid Device Structure by Aqueous Chemical Method

Advanced Materials Research ◽

10.4028/www.scientific.net/amr.123-125.779 ◽

2010 ◽

Vol 123-125 ◽

pp. 779-782 ◽

Cited By ~ 4

Author(s):

P. Suresh Kumar ◽

J. Sundaramurthy ◽

D. Mangalaraj ◽

D. Rajarathnam ◽

M.P. Srinivasan

Keyword(s):

Zno Nanorods ◽

Solution Process ◽

Hexagonal Wurtzite Structure ◽

Device Structure ◽

Axis Orientation ◽

Light Emitting ◽

Hybrid Device ◽

Uv Emission ◽

Heterojunction Device ◽

Cbd Method

In the present work, vertical ZnO nanorods (NRs) were grown onto ITO substrates by a simple two step chemical process at relatively low temperature by using successive ionic layer absorption and reaction method (SILAR) and chemical bath deposition (CBD) method. The investigated on n- ZnO/ p-Polythiophene heterojunction device have been fabricated with ZnO nanorods. Structural analysis reveals that the grown ZnO NRs exhibit (002) reflection with higher intensity, indicating that the ZnO NRs grown in c-axis orientation. FESEM image shows the surface morphology of grown ZnO nanorods was of hexagonal wurtzite structure whose diameter varies from 200 nm to 1μm. Room temperature Photoluminescence exhibited strong UV emission at ∼386 nm and a negligible green band confirms the presence of very low concentration of oxygen vacancies in the well-aligned ZnO nanorods. The current–voltage (I –V) characteristics of the heterojunctions show good rectifying diode characteristics. These results indicate that hybrid device fabricated from solution process is a promising approach for future light-emitting diodes (LEDs) devices.

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ZnO Nanostructured Diodes: The Influence of Synthesis Conditions and p-type Material on Device Performance

MRS Proceedings ◽

10.1557/opl.2012.1153 ◽

2012 ◽

Vol 1439 ◽

pp. 95-100

Author(s):

S.M. Hatch ◽

S. Dunn

Keyword(s):

Zno Nanorods ◽

Type Material ◽

Device Performance ◽

Processing Conditions ◽

Synthesis Conditions ◽

Hybrid Device ◽

Turn On ◽

Type Layer ◽

Hybrid Devices ◽

P Type

ABSTRACTWe produce four distinct ZnO nanorod diode structures that are based on ZnO nanorods produced at pH 6 and pH 11 and have the p-type material PEDOT:PSS (hybrid device) or CuSCN (all inorganic device). After testing the performance of the diodes we show a rectification of 1050 at ±1V in the dark for the inorganic device. The device also exhibits good UV photodetection showing a rapid ca0.1ms turn on and off to a source of illumination. The hybrid devices performed as previously reported with a rectification of 25 at ±1V in both dark and under illumination. We ascribe the performance of the devices to the differences in morphology in the ZnO brought about by the processing conditions and the way in which the p-type layer coats the nanostructure.

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Particle characterization of CVD tungsten metallization for 64 MBIT DRAM

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s0424820100088798 ◽

1991 ◽

Vol 49 ◽

pp. 896-897

Author(s):

Marylyn Bennett-Lilley ◽

Thomas T.H. Fu ◽

David D. Yin ◽

R. Allen Bowling

Keyword(s):

Chemical Vapor ◽

Device Performance ◽

Particle Characterization ◽

Particle Generation ◽

Tungsten Hexafluoride ◽

Homogeneous Particle ◽

Multiple Levels ◽

Circuit Density ◽

Sources Of Contamination

Chemical Vapor Deposition (CVD) tungsten metallization is used to increase VLSI device performance due to its low resistivity, and improved reliability over other metallization schemes. Because of its conformal nature as a blanket film, CVD-W has been adapted to multiple levels of metal which increases circuit density. It has been used to fabricate 16 MBIT DRAM technology in a manufacturing environment, and is the metallization for 64 MBIT DRAM technology currently under development. In this work, we investigate some sources of contamination. One possible source of contamination is impurities in the feed tungsten hexafluoride (WF6) gas. Another is particle generation from the various reactor components. Another generation source is homogeneous particle generation of particles from the WF6 gas itself. The purpose of this work is to investigate and analyze CVD-W process-generated particles, and establish a particle characterization methodology.

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In situ TEM measurements of the electrical properties of interface dislocations

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s0424820100131322 ◽

1992 ◽

Vol 50 (2) ◽

pp. 1338-1339

Author(s):

F. M. Ross ◽

R. Hull ◽

D. Bahnck ◽

J. C. Bean ◽

L. J. Peticolas ◽

...

Keyword(s):

Electrical Properties ◽

Electronic Device ◽

In Situ Tem ◽

Device Performance ◽

Misfit Dislocations ◽

Electrical Characteristics ◽

Strained Layer ◽

Transmission Electron ◽

Interfacial Dislocations

We describe an investigation of the electrical properties of interfacial dislocations in strained layer heterostructures. We have been measuring both the structural and electrical characteristics of strained layer p-n junction diodes simultaneously in a transmission electron microscope, enabling us to correlate changes in the electrical characteristics of a device with the formation of dislocations.The presence of dislocations within an electronic device is known to degrade the device performance. This degradation is of increasing significance in the design and processing of novel strained layer devices which may require layer thicknesses above the critical thickness (hc), where it is energetically favourable for the layers to relax by the formation of misfit dislocations at the strained interfaces. In order to quantify how device performance is affected when relaxation occurs we have therefore been investigating the electrical properties of dislocations at the p-n junction in Si/GeSi diodes.

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Charging microscopy and cathodoluminescence imaging of semi-insulating gallium arsenide

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s042482010014542x ◽

1986 ◽

Vol 44 ◽

pp. 816-817

Author(s):

T.C. Sheu ◽

S. Myhajlenko ◽

D. Davito ◽

J.L. Edwards ◽

R. Roedel ◽

...

Keyword(s):

Integrated Circuits ◽

Secondary Electron ◽

Crystal Defects ◽

Device Performance ◽

Gaas Wafer ◽

Surface Charging ◽

Gaas Substrates ◽

Voltage Contrast ◽

Cathodoluminescence Imaging ◽

Scanning Electron

Liquid encapsulated Czochralski (LEC) semi-insulating (SI) GaAs has applications in integrated optics and integrated circuits. Yield and device performance is dependent on the homogeniety of the wafers. Therefore, it is important to characterise the uniformity of the GaAs substrates. In this respect, cathodoluminescence (CL) has been used to detect the presence of crystal defects and growth striations. However, when SI GaAs is examined in a scanning electron microscope (SEM), there will be a tendency for the surface to charge up. The surface charging affects the backscattered and secondary electron (SE) yield. Local variations in the surface charge will give rise to contrast (effectively voltage contrast) in the SE image. This may be associated with non-uniformities in the spatial distribution of resistivity. Wakefield et al have made use of “charging microscopy” to reveal resistivity variations across a SI GaAs wafer. In this work we report on CL imaging, the conditions used to obtain “charged” SE images and some aspects of the contrast behaviour.

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