Failure analysis of admiralty brass tubes in a surface condenser: a case study at the petrochemical industry

Abstract This paper presents the failure analysis on a 1.5m flex harness for a space flight instrument that exhibited two failure modes: global isolation resistances between all adjacent traces measured tens of milliohm and lower resistance on the order of 1 kiloohm was observed on several pins. It shows a novel method using a temperature controlled air stream while monitoring isolation resistance to identify a general area of interest of a low isolation resistance failure. The paper explains how isolation resistance measurements were taken and details the steps taken in both destructive and non-destructive analyses. In theory, infrared hotspot could have been completed along the length of the flex harness to locate the failure site. However, with a field of view of approximately 5 x 5 cm, this technique would have been time prohibitive.

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Failure Analysis of CDM-ESD Damage in a GaAs RFIC

ISTFA 2000: Conference Proceedings from the 26th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2000p0215 ◽

2000 ◽

Author(s):

Amy Poe ◽

Steve Brockett ◽

Tony Rubalcava

Keyword(s):

Radio Frequency ◽

Failure Analysis ◽

Integrated Circuit ◽

Production Test ◽

Analysis Techniques ◽

Device Model ◽

Charged Device ◽

Subsequent Failure

Abstract The intent of this work is to demonstrate the importance of charged device model (CDM) ESD testing and characterization by presenting a case study of a situation in which CDM testing proved invaluable in establishing the reliability of a GaAs radio frequency integrated circuit (RFIC). The problem originated when a sample of passing devices was retested to the final production test. Nine of the 200 sampled devices failed the retest, thus placing the reliability of all of the devices in question. The subsequent failure analysis indicated that the devices failed due to a short on one of two capacitors, bringing into question the reliability of the dielectric. Previous ESD characterization of the part had shown that a certain resistor was likely to fail at thresholds well below the level at which any capacitors were damaged. This paper will discuss the failure analysis techniques which were used and the testing performed to verify the failures were actually due to ESD, and not caused by weak capacitors.

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Advanced IR-OBIRCH Analysis Technique for High Isb Failure Analysis

ISTFA 2010: Conference Proceedings from the 36th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2010p0233 ◽

2010 ◽

Author(s):

Kuo Hsiung Chen ◽

Wen Sheng Wu ◽

Yu Hsiang Shu ◽

Jian Chan Lin

Keyword(s):

Failure Analysis ◽

Failure Mechanisms ◽

Fault Localization ◽

Resistance Change ◽

The Real ◽

Analysis Techniques ◽

Analysis Technique ◽

Leakage Failure ◽

Failure Site

Abstract IR-OBIRCH (Infrared Ray – Optical Beam Induced Resistance Change) is one of the main failure analysis techniques [1] [2] [3] [4]. It is a useful tool to do fault localization on leakage failure cases such as poor Via or contact connection, FEoL or BEoL pattern bridge, and etc. But the real failure sites associated with the above failure mechanisms are not always found at the OBIRCH spot locations. Sometimes the real failure site is far away from the OBIRCH spot and it will result in inconclusive PFA Analysis. Finding the real failure site is what matters the most for fault localization detection. In this paper, we will introduce one case using deep sub-micron process generation which suffers serious high Isb current at wafer donut region. In this case study a BEoL Via poor connection is found far away from the OBIRCH spots. This implies that layout tracing skill and relation investigation among OBIRCH spots are needed for successful failure analysis.

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The Electrical Characterization and Physical Failure Analysis for Transistor Gate Leakage

ISTFA 2006: Conference Proceedings from the 32nd International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2006p0257 ◽

2006 ◽

Author(s):

Tsung-Te Li ◽

Chao-Chi Wu ◽

Jung-Hsiang Chuang ◽

Jon C. Lee

Keyword(s):

Failure Analysis ◽

Electrical Characterization ◽

Physical Analysis ◽

Gate Leakage ◽

Force Microscopy ◽

Atomic Force ◽

Transmission Electron ◽

Voltage Stress ◽

Leakage Site

Abstract This article describes the electrical and physical analysis of gate leakage in nanometer transistors using conducting atomic force microscopy (C-AFM), nano-probing, transmission electron microscopy (TEM), and chemical decoration on simulated overstressed devices. A failure analysis case study involving a soft single bit failure is detailed. Following the nano-probing analysis, TEM cross sectioning of this failing device was performed. A voltage bias was applied to exaggerate the gate leakage site. Following this deliberate voltage overstress, a solution of boiling 10%wt KOH was used to etch decorate the gate leakage site followed by SEM inspection. Different transistor leakage behaviors can be identified with nano-probing measurements and then compared with simulation data for increased confidence in the failure analysis result. Nano-probing can be used to apply voltage stress on a transistor or a leakage path to worsen the weak point and then observe the leakage site easier.

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Case Study in Fault Isolation of a Metal Short for Yield Enhancement

ISTFA 2010: Conference Proceedings from the 36th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2010p0049 ◽

2010 ◽

Author(s):

Sarven Ipek ◽

David Grosjean

Keyword(s):

Failure Analysis ◽

Failure Mechanism ◽

Photon Emission ◽

Fault Isolation ◽

Yield Enhancement ◽

Analysis Technique ◽

Laser Signal ◽

Signal Injection ◽

Microscopy Techniques

Abstract The application of an individual failure analysis technique rarely provides the failure mechanism. More typically, the results of numerous techniques need to be combined and considered to locate and verify the correct failure mechanism. This paper describes a particular case in which different microscopy techniques (photon emission, laser signal injection, and current imaging) gave clues to the problem, which then needed to be combined with manual probing and a thorough understanding of the circuit to locate the defect. By combining probing of that circuit block with the mapping and emission results, the authors were able to understand the photon emission spots and the laser signal injection microscopy (LSIM) signatures to be effects of the defect. It also helped them narrow down the search for the defect so that LSIM on a small part of the circuit could lead to the actual defect.

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Die-Level Scanning Capacitance Microscopy Fault Isolation on SOI Fin-FET Devices for Advanced Semiconductor Nodes

10.31399/asm.cp.istfa2018p0543 ◽

2018 ◽

Author(s):

Lucile C. Teague Sheridan ◽

Tanya Schaeffer ◽

Yuting Wei ◽

Satish Kodali ◽

Chong Khiam Oh

Keyword(s):

Atomic Force Microscopy ◽

Failure Analysis ◽

Fault Isolation ◽

Scanning Capacitance Microscopy ◽

Force Microscopy ◽

Atomic Force

Abstract It is widely acknowledged that Atomic force microscopy (AFM) methods such as conductive probe AFM (CAFM) and Scanning Capacitance Microscopy (SCM) are valuable tools for semiconductor failure analysis. One of the main advantages of these techniques is the ability to provide localized, die-level fault isolation over an area of several microns much faster than conventional nanoprobing methods. SCM, has advantages over CAFM in that it is not limited to bulk technologies and can be utilized for fault isolation on SOI-based technologies. Herein, we present a case-study of SCM die-level fault isolation on SOI-based FinFET technology at the 14nm node.

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Laser Voltage Imaging: A New Perspective of Laser Voltage Probing

ISTFA 2010: Conference Proceedings from the 36th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2010p0005 ◽

2010 ◽

Author(s):

Yin S. Ng ◽

Ted Lundquist ◽

Dmitry Skvortsov ◽

Joy Liao ◽

Steven Kasapi ◽

...

Keyword(s):

Failure Analysis ◽

Functional Failure ◽

Voltage Imaging ◽

Laser Probing ◽

New Perspective

Abstract Laser Voltage Imaging (LVI) is a new application developed from Laser Voltage Probing (LVP). Most LVP applications have focused on design debug or design characterization, and are seldom used for global functional failure analysis. LVI enables the failure analysis engineer to utilize laser probing techniques in the failure analysis realm. In this paper, we present LVI as an emerging FA technique. We will discuss setting up an LVI acquisition and present its current challenges. Finally, we will present an LVI application in the form of a case study.

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Case Study—Failure Analysis of a Multiplexer

ISTFA 2016: Conference Proceedings from the 42nd International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2016p0243 ◽

2016 ◽

Author(s):

Michael Woo ◽

Marcos Campos ◽

Luigi Aranda

Keyword(s):

Failure Analysis ◽

High Reliability ◽

Component Failure ◽

Root Cause ◽

Knowing That ◽

Cause Of Failure ◽

The Cost

Abstract A component failure has the potential to significantly impact the cost, manufacturing schedule, and/or the perceived reliability of a system, especially if the root cause of the failure is not known. A failure analysis is often key to mitigating the effects of a componentlevel failure to a customer or a system; minimizing schedule slips, minimizing related accrued costs to the customer, and allowing for the completion of the system with confidence that the reliability of the product had not been compromised. This case study will show how a detailed and systemic failure analysis was able to determine the exact cause of failure of a multiplexer in a high-reliability system, which allowed the manufacturer to confidently proceed with production knowing that the failure was not a systemic issue, but rather that it was a random “one time” event.

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Root Cause Analysis for Pin Leakage

ISTFA 2016: Conference Proceedings from the 42nd International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2016p0217 ◽

2016 ◽

Author(s):

Zhigang Song ◽

Jochonia Nxumalo ◽

Manuel Villalobos ◽

Sweta Pendyala

Keyword(s):

Failure Analysis ◽

Root Cause Analysis ◽

Advanced Technology ◽

Process Step ◽

Cause Analysis ◽

Hard Mask ◽

Technology Node ◽

Root Cause ◽

Tools And Techniques

Abstract Pin leakage continues to be on the list of top yield detractors for microelectronics devices. It is simply manifested as elevated current with one pin or several pins during pin continuity test. Although many techniques are capable to globally localize the fault of pin leakage, root cause analysis and identification for it are still very challenging with today’s advanced failure analysis tools and techniques. It is because pin leakage can be caused by any type of defect, at any layer in the device and at any process step. This paper presents a case study to demonstrate how to combine multiple techniques to accurately identify the root cause of a pin leakage issue for a device manufactured using advanced technology node. The root cause was identified as under-etch issue during P+ implantation hard mask opening for ESD protection diode, causing P+ implantation missing, which was responsible for the nearly ohmic type pin leakage.

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