Field Effect Transistors-A review of their growth and the state of the art

1975 ◽  
Vol 16 (3) ◽  
pp. 126-132
Author(s):  
D. S. Kushwah
2012 ◽  
Vol 1439 ◽  
pp. 101-107
Author(s):  
Guillaume Rosaz ◽  
Bassem Salem ◽  
Nicolas Pauc ◽  
Pascal Gentile ◽  
Priyanka Periwal ◽  
...  

ABSTRACTThe authors present the technological routes used to build planar and vertical gate all-around (GAA) field-effect transistors (FETs) using both Si and SiGe nanowires (NWs) and the electrical performances of the as-obtained components. Planar FETs are characterized in back gate configuration and exhibit good behavior such as an ION/IOFF ratio up to 106. Hysteretic behavior and sub-threshold slope values with respect to surface and oxide interface trap densities are discussed. Vertical devices using Si NWs show good characteristics at the state of the art with ION/IOFF ratio close to 106 and sub-threshold slope around 125 mV/decade while vertical SiGe devices also obtained with the same technological processes, present an ION/IOFF ratio from 103 to 104but with poor dynamics which can be explained by the high interface traps density.


2019 ◽  
Vol 10 (1) ◽  
Author(s):  
Monica Bollani ◽  
Marco Salvalaglio ◽  
Abdennacer Benali ◽  
Mohammed Bouabdellaoui ◽  
Meher Naffouti ◽  
...  

AbstractLarge-scale, defect-free, micro- and nano-circuits with controlled inter-connections represent the nexus between electronic and photonic components. However, their fabrication over large scales often requires demanding procedures that are hardly scalable. Here we synthesize arrays of parallel ultra-long (up to 0.75 mm), monocrystalline, silicon-based nano-wires and complex, connected circuits exploiting low-resolution etching and annealing of thin silicon films on insulator. Phase field simulations reveal that crystal faceting and stabilization of the wires against breaking is due to surface energy anisotropy. Wires splitting, inter-connections and direction are independently managed by engineering the dewetting fronts and exploiting the spontaneous formation of kinks. Finally, we fabricate field-effect transistors with state-of-the-art trans-conductance and electron mobility. Beyond the first experimental evidence of controlled dewetting of patches featuring a record aspect ratio of $$\sim$$~1/60000 and self-assembled $$\sim$$~mm long nano-wires, our method constitutes a distinct and promising approach for the deterministic implementation of atomically-smooth, mono-crystalline electronic and photonic circuits.


2016 ◽  
Vol 1 (5) ◽  
pp. 1600090 ◽  
Author(s):  
Inés Temiño ◽  
Freddy G. Del Pozo ◽  
M. R. Ajayakumar ◽  
Sergi Galindo ◽  
Joaquim Puigdollers ◽  
...  

Science ◽  
2018 ◽  
Vol 361 (6400) ◽  
pp. 387-392 ◽  
Author(s):  
Chenguang Qiu ◽  
Fei Liu ◽  
Lin Xu ◽  
Bing Deng ◽  
Mengmeng Xiao ◽  
...  

An efficient way to reduce the power consumption of electronic devices is to lower the supply voltage, but this voltage is restricted by the thermionic limit of subthreshold swing (SS), 60 millivolts per decade, in field-effect transistors (FETs). We show that a graphene Dirac source (DS) with a much narrower electron density distribution around the Fermi level than that of conventional FETs can lower SS. A DS-FET with a carbon nanotube channel provided an average SS of 40 millivolts per decade over four decades of current at room temperature and high device current I60 of up to 40 microamperes per micrometer at 60 millivolts per decade. When compared with state-of-the-art silicon 14-nanometer node FETs, a similar on-state current Ion is realized but at a much lower supply voltage of 0.5 volts (versus 0.7 volts for silicon) and a much steeper SS below 35 millivolts per decade in the off-state.


Author(s):  
Mehdi Bagherizadeh ◽  
Mona Moradi ◽  
Mostafa Torabi

<p>Compressor cell is often placed in critical path of multiplier circuits to perform partial product summation. Therefore it plays a significant role in determining the entire performance of multiplier and digital system. Respecting to the necessity of low power design for portable electronic, designing a low power and high performance compressors seems to be a good solution to overcome of these problems for computations. In this paper a novel high performance four-to-two compressor cell is proposed using Carbon Nanotube Field Effect Transistors (CNTFETs) technology. The new cell is based on Majority Function, NOR, and NAND gates. The main advantage of proposed design in comparison with former cells is the ease of obtaining CARRY output by means of Majority function. Simulations have been done with 32nm technology node using Synopsys HSPICE software. Simulation results confirm the priority of the proposed cell compared to other state-of-the-art four-to-two compressor cells.</p>


2012 ◽  
Vol 1407 ◽  
Author(s):  
T. Uchino ◽  
G. N. Ayre ◽  
D. C. Smith ◽  
J. L. Hutchison ◽  
C. H. de Groot ◽  
...  

ABSTRACTThe metal-catalyst-free growth of carbon nanotubes (CNTs) using chemical vapor deposition and the application in field-effect transistors (FETs) is presented. The CNT growth process used a 3-nm-thick Ge layer on SiO2 that was subsequently annealed to produce Ge nanoparticles. Raman measurements show the presence of radial breathing mode (RBM) peaks and the absence of the disorder induced D-band, indicating single walled CNTs (SWNTs) with a low defect density. The synthesized CNTs are used to fabricate CNTFETs and the best device has a state-of-the-art on/off current ratio of 3×108 and a steep sub-threshold slope of 110 mV/decade.


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