Conductive bridge random access memory characteristics of SiCN based transparent device due to indium diffusion

2018 ◽  
Vol 29 (12) ◽  
pp. 125202 ◽  
Author(s):  
Dayanand Kumar ◽  
Rakesh Aluguri ◽  
Umesh Chand ◽  
Tseung-Yuen Tseng
2019 ◽  
Vol 13 (11) ◽  
pp. 1900285 ◽  
Author(s):  
Hao-Xuan Zheng ◽  
Chih-Cheng Shih ◽  
Ting-Chang Chang ◽  
Lin-Yi Shih ◽  
Yao-Kai Shih ◽  
...  

2015 ◽  
Vol 106 (15) ◽  
pp. 159901
Author(s):  
Meiyun Zhang ◽  
Shibing Long ◽  
Guoming Wang ◽  
Xiaoxin Xu ◽  
Yang Li ◽  
...  

2015 ◽  
Vol 36 (2) ◽  
pp. 129-131 ◽  
Author(s):  
Xiaoxin Xu ◽  
Hangbing Lv ◽  
Hongtao Liu ◽  
Tiancheng Gong ◽  
Guoming Wang ◽  
...  

2021 ◽  
Vol 21 (8) ◽  
pp. 4216-4222
Author(s):  
Songyi Yoo ◽  
In-Man Kang ◽  
Sung-Jae Cho ◽  
Wookyung Sun ◽  
Hyungsoon Shin

A capacitorless one-transistor dynamic random-access memory cell with a polysilicon body (poly-Si 1T-DRAM) has a cost-effective fabrication process and allows a three-dimensional stacked architecture that increases the integration density of memory cells. Also, since this device uses grain boundaries (GBs) as a storage region, it can be operated as a memory cell even in a thin body device. GBs are important to the memory characteristics of poly-Si 1T-DRAM because the amount of trapped charge in the GBs determines the memory’s data state. In this paper, we report on a statistical analysis of the memory characteristics of poly-Si 1T-DRAM cells according to the number and location of GBs using TCAD simulation. As the number of GBs increases, the sensing margin and retention time of memory cells deteriorate due to increasing trapped electron charge. Also, “0” state current increases and memory performance degrades in cells where all GBs are adjacent to the source or drain junction side in a strong electric field. These results mean that in poly-Si 1T-DRAM design, the number and location of GBs in a channel should be considered for optimal memory performance.


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