scholarly journals Low-power LDO Design of High-efficiency Class AB OTA Based on Adaptive Biasing

2021 ◽  
Vol 1754 (1) ◽  
pp. 012058
Author(s):  
Hao Yang ◽  
Shengming Huang ◽  
Quanzhen Duan
Keyword(s):  
Low Power ◽  
High Efficiency ◽  
Class Ab ◽  
Adaptive Biasing

scholarly journals High-Speed Rail-to-Rail Class-AB Buffer Amplifier with Compact, Adaptive Biasing for FPD Applications

Electronics ◽  
2020 ◽  
Vol 9 (12) ◽  
pp. 2018
Author(s):  
Chang-Ho An ◽  
Bai-Sun Kong
Keyword(s):  
Low Power ◽  
Current Source ◽  
Settling Time ◽  
Output Buffer ◽  
Slew Rate ◽  
Class Ab ◽  
Tail Current ◽  
Rail To Rail ◽  
Adaptive Biasing ◽  
Buffer Amplifier

A high-slew-rate, low-power, CMOS, rail-to-rail buffer amplifier for large flat-panel-display (FPD) applications is proposed. The major circuit of the output buffer is a rail-to-rail, folded-cascode, class-AB amplifier which can control the tail current source using a compact, novel, adaptive biasing scheme. The proposed output buffer amplifier enhances the slew rate throughout the entire rail-to-rail input signal range. To obtain a high slew rate and low power consumption without increasing the static current, the tail current source of the adaptive biasing generates extra current during the transition time of the output buffer amplifier. A column driver IC incorporating the proposed buffer amplifier was fabricated in a 1.6-μm 18-V CMOS technology, whose evaluation results indicated that the static current was reduced by up to 39.2% when providing an identical settling time. The proposed amplifier also achieved up to 49.1% (90% falling) and 19.9 % (99.9% falling) improvements in terms of settling time for almost the same static current drawn and active area occupied.

scholarly journals Low Power Cusped Field Thruster Developed for the Space-Borne Gravitational Wave Detection Mission in China

2021 ◽  
Vol 11 (14) ◽  
pp. 6549
Author(s):  
Hui Liu ◽  
Ming Zeng ◽  
Xiang Niu ◽  
Hongyan Huang ◽  
Daren Yu
Keyword(s):  
Low Power ◽  
Gravitational Wave ◽  
Attitude Control ◽  
High Efficiency ◽  
Experimental Investigations ◽  
Attitude Control System ◽  
Gravitational Wave Detection ◽  
Wave Detection ◽  
Wide Range ◽  
Institute Of Technology

The microthruster is the crucial device of the drag-free attitude control system, essential for the space-borne gravitational wave detection mission. The cusped field thruster (also called the High Efficiency Multistage Plasma Thruster) becomes one of the candidate thrusters for the mission due to its low complexity and potential long life over a wide range of thrust. However, the prescribed minimum of thrust and thrust noise are considerable obstacles to downscaling works on cusped field thrusters. This article reviews the development of the low power cusped field thruster at the Harbin Institute of Technology since 2012, including the design of prototypes, experimental investigations and simulation studies. Progress has been made on the downscaling of cusped field thrusters, and a new concept of microwave discharge cusped field thruster has been introduced.

Self-Reduction Quiescent Current Low Power Low Dropout Regulator for SoC Application

2012 ◽  
Vol 591-593 ◽  
pp. 2632-2635
Author(s):  
Lee Chu Liang ◽  
Roslina Mohd Sidek
Keyword(s):  
Low Power ◽  
Process Model ◽  
High Efficiency ◽  
System Stability ◽  
Cmos Process ◽  
Output Impedance ◽  
Load Current ◽  
Output Load ◽  
Quiescent Current ◽  
Low Dropout Regulator

A low power low-dropout (LDO) voltage regulator with self-reduction quiescent current is proposed in this paper. This proposed capacitorless LDO for Silicon-on-Chip (SoC) application has introduced a self-adjustable low-impedance circuitry at the output of LDO to attain stability critically during low output load current (less than a few hundred of micro-ampere). When the LDO load current increases, it reduces the LDO output impedance and moved the pole towards higher frequency away from the dominant pole and improving the system stability. When this happen, less amount of quiescent current is needed for the low-impedance circuitry to sustain the low output impedance. In this proposed LDO, the quiescent current that been used to sustain the low output impedance will be self-reduced when the output load current increases. Thus, the reduction of quiescent current at low output load current has tremendously improved the efficiency. The simulation results have shown a promising stability at low load current 0~1mA. The dropout voltage for this LDO is only 100mV at 1.2V supply. The proposed LDO is validated using Silterra 0.13μm CMOS process model and designed with high efficiency at low output load current.

scholarly journals Wireless Energy Transfer

2015 ◽  
pp. 63-91
Author(s):  
Aya Mabrouki ◽  
Mohamed Latrach
Keyword(s):  
Energy Transfer ◽  
Energy Harvesting ◽  
Low Power ◽  
High Efficiency ◽  
Microwave Energy ◽  
Wireless Energy Transfer ◽  
Design Considerations ◽  
High Efficient ◽  
Harvesting Techniques ◽  
Power Rectifier

This chapter proposes an overview of microwave energy harvesting with focuses on the design of high efficiency low power rectifying circuits. A background survey of RF energy harvesting techniques is presented first. Then, the performances of conventional rectifier topologies are analyzed and discussed. A review of the most efficient rectenna designs, from the state of the art, is also presented. Design considerations for low power rectifier operations are detailed and new high efficient rectifying circuits are designed and evaluated in both GSM and ISM bands under low power constraints.

scholarly journals Low Power AVLS-TSPC based 2/3 Pre-Scaler

2019 ◽  
Vol 9 (1) ◽  
pp. 6687-6693
Keyword(s):  
Low Power ◽  
High Efficiency ◽  
Supply Voltage ◽  
Low Frequency ◽  
Cmos Technology ◽  
Frequency Signal ◽  
High Frequency Signal ◽  
Power Requirement ◽  
Fast Pace ◽  
Integer Division

The technology has grown at an ultra-fast pace along with the world. Small devices with less power and high efficiency are in demand. As the circuit size gets smaller, the power requirement increases due to a greater number of transistors. A pre-scaler is a circuit which reduces the high frequency signal to a low frequency signal by integer division. A new approach to low power pre-scaler is proposed in this paper, which is an add-on to the conventional pre-scaler circuit. A true single-phase clock (TSPC) circuit reduces the skew problems in the clock and is used to realize latches and flip-flops. The objective of low power is fulfilled by incorporating the Adaptive Voltage Level Source (AVLS) to TSPC based circuit. The proposed AVLS-TSPC based pre-scaler was analyzed for a frequency of 10 MHz with a supply voltage of 1.8 V for both divide by 2 and 3 modes. The proposed pre-scaler consumes considerably lesser power when compared to that of the existing pre-scaler circuit. The circuits are implemented in 180 nm CMOS technology using Cadence Virtuoso and simulated using Cadence Spectre.

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