Investigation of leakage current and breakdown voltage in irradiated double-sided 3D silicon sensors

2016 ◽  
Vol 11 (09) ◽  
pp. P09006-P09006 ◽  
Author(s):  
G.-F. Dalla Betta ◽  
N. Ayllon ◽  
M. Boscardin ◽  
M. Hoeferkamp ◽  
S. Mattiazzo ◽  
...  
2007 ◽  
Vol 336-338 ◽  
pp. 680-683
Author(s):  
Jing Nan Cai ◽  
Yuan Hua Lin ◽  
Rong Juan Zhao ◽  
Ce Wen Nan ◽  
Jin Liang He

ZnO-Pr6O11-Dy2O3-based varistor ceramics doped with 0~1.5 mol% La2O3 were fabricated by a conventional ceramic method. All the samples were sintered at 1350 oCfor 2 h. The phase composition and microstructure of the ceramic samples have been investigated by XRD, SEM and EDS. The results of SEM micrographs indicated that the La2O3 additives can promote ZnO grain’s growth, and the rare earth elements dispersed mainly in the intergranular phase observed by EDS. The electrical properties of the samples determined by the V-I curves revealed that the breakdown voltage of samples decreases from 508 V/mm to about 100 V/mm with the increase of La2O3, and the nonlinear exponent also decreases from 20.2 to 13.2. The typical leakage current is about 10.2 μA for the sample doped with 0.5 mol% La2O3.


2007 ◽  
Vol 134 ◽  
pp. 379-382
Author(s):  
Claire Therese Richard ◽  
D. Benoit ◽  
S. Cremer ◽  
L. Dubost ◽  
B. Iteprat ◽  
...  

3D architecture is an alternative way to high-k dielectric to increase the capacitance of MIM structure. However, the top of this kind of structure is very sensitive to defectivity and then requires a special wet treatment. In this paper, we present the process flow for a 3D MIM integration in a CMOS copper back-end and a two steps wet process which provides very good electrical performances, i.e. leakage current lower than 10-9A.cm-2 at 5V / 125°C and breakdown voltage higher than 20V. At first, a SC1 step is done for electrode isolation improvement by material etching with good selectivity towards dielectric: that’s the electrode recess. In the second time, a HF step is done for copper oxide dilution and residues removal from the top of the 3D structure.


1990 ◽  
Author(s):  
Tai Ping Sun ◽  
Si-Chen Lee ◽  
Kou-Chen Liu ◽  
Sheng-Jehn Yang

2018 ◽  
Vol 924 ◽  
pp. 84-87 ◽  
Author(s):  
Nicolò Piluso ◽  
Andrea Severino ◽  
Ruggero Anzalone ◽  
Maria Ausilia di Stefano ◽  
Enzo Fontana ◽  
...  

In this work the deposition of buffer layer has been studied in order to increase the quality of the epitaxial layer and improve the performance of device. The comparison between two different thicknesses of buffer layer reveals a decrease of crystallographic defects and an improvement of electrical parameters of MOSFET device as leakage current and breakdown voltage.


2011 ◽  
Vol 58 (7) ◽  
pp. 1986-1994 ◽  
Author(s):  
Wei Lu ◽  
Lingquan Wang ◽  
Siyuan Gu ◽  
David P. R. Aplin ◽  
Daniel M. Estrada ◽  
...  

2014 ◽  
Vol 7 (4) ◽  
pp. 041003 ◽  
Author(s):  
Joseph J. Freedsman ◽  
Takashi Egawa ◽  
Yuya Yamaoka ◽  
Yoshiki Yano ◽  
Akinori Ubukata ◽  
...  

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