Asymmetric Slope Dual Mode Differential Logic Circuit for Compatibility of Low-Power and High-Speed Operations

The lowering of power consumption in CMOS VLSI digital systems is one of the most important problems that appear now for developers of CAD systems. One of the effective approaches to lowering the dynamic power consumption is creation of an algorithmic description of the VHDL project, which provides for the deactivation of some functional blocks which are not necessary in particular moments. Contemporary synthesizers fulfill the high level synthesis of logic circuits by substitution of description of each VHDL construction with functionally structural description of a proper logic subcircuit. The results of digital logic circuit synthesis (the number of logic elements and power consumption) depend significantly on initial VHDL code. During initial VHDL code development it is possible to use different approaches to improve some parameters of synthesized logic circuit. At the algorithmic level of the digital design, it is necessary to provide for disconnection of the units, which cause the higher power consumption. In this paper such methods of algorithmic VHDL description of logic circuit are studied. The efficiency of the proposed methods is compared with the traditional method of VHDL-description which does not take the aspect of power consumption into account and is oriented only to the correct functionality of the developed logic circuit. To estimate the power consumption of logic circuits the approach is used which allows applying high-speed logical VHDL-simulation of structural descriptions (netlists) of logic circuits instead of slow SPICE simulation. The main conclusion of the provided study is the following: the clock gating and the storage of operand values for complex operations as well as zero value setting for simple ones are effective methods for the VHDL description of operational units with low power consumption implemented in the CMOS basis.

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Review on Domino Logic Techniques for High Speed Low-Power Logic Circuit Application

2019 5th International Conference on Advanced Computing & Communication Systems (ICACCS) ◽

10.1109/icaccs.2019.8728425 ◽

2019 ◽

Author(s):

T. Vinoth Bala ◽

P. L. Rishi ◽

R. Sharuya ◽

N. Subashree ◽

M. Sneha ◽

...

Keyword(s):

Low Power ◽

High Speed ◽

Logic Circuit ◽

Domino Logic ◽

Low Power Logic

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A low power high speed error correction code macro using complementary pass transistor logic circuit

Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334) ◽

10.1109/asic.1997.616970 ◽

2002 ◽

Cited By ~ 2

Author(s):

L.K. Wang ◽

H.H. Chen

Keyword(s):

Low Power ◽

Error Correction ◽

High Speed ◽

Logic Circuit ◽

Error Correction Code ◽

Speed Error ◽

Pass Transistor ◽

Pass Transistor Logic

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1.1 V high speed, low power BiCMOS logic circuit

Electronics Letters ◽

10.1049/el:19950714 ◽

1995 ◽

Vol 31 (13) ◽

pp. 1039-1041 ◽

Cited By ~ 5

Author(s):

Yeo Kiat Seng ◽

S.S. Rofail

Keyword(s):

Low Power ◽

High Speed ◽

Logic Circuit

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Energy Efficient Digital Circuits using Two Phase Clocking Sub-Threshold Adiabatic Logic

International Journal of Recent Technology and Engineering - 2 ◽

10.35940/ijrte.b1692.078219 ◽

2019 ◽

Vol 8 (2) ◽

pp. 101-106

Keyword(s):

Low Power ◽

High Speed ◽

Digital Circuits ◽

Vlsi Design ◽

Logic Circuit ◽

Oxide Semiconductor ◽

Process Technology ◽

Two Phase ◽

Adiabatic Logic ◽

On Chip

Power is a major constraint in Digital VLSI circuits, due to reduction in sizes of Metal Oxide Semiconductor (MOS) transistors are scaling down. Low-power technologies are used to diminish the power utilization be able to be classified as Sub-threshold CMOS and Adiabatic logic tachniques. In, Sub-threshold CMOS defines a system which reduces the power utilization to inferior than the threshold voltage of a MOS Device, where as Adiabatic logic circuit is a method which minimizes the energy usage through suppress the applied voltage to the resistance of a given VLSI design. This effort deals to offer a subthreshold adiabatic logic circuit of low power CMOS circuits that uses 2φ clocking subthreshold Adiabatic Logic. The digital circuits were designed in HSPICE using 0.18 μm CMOS standard process technology. It is evident from the results that the 2φ Clocking Subthreshold Adiabatic design is beneficial in major application where power starving is of major significance at the same time as in elevated its performance efficiency in DSP processor IC, System on chip, Network on chip and High speed digital ICs.

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