Threshold voltage sensitivity of 0.1 μm channel length fully-depleted SOI NMOSFET's with back-gate bias

1995 ◽  
Vol 42 (9) ◽  
pp. 1707-1709 ◽  
Author(s):  
E. Leobandung ◽  
S.Y. Chou
Keyword(s):  
Threshold Voltage ◽  
Channel Length ◽  
Voltage Sensitivity ◽  
Gate Bias ◽  
Back Gate ◽  
Fully Depleted

Back gate effects on threshold voltage sensitivity to SOI thickness in fully-depleted SOI MOSFETs

2001 ◽  
Vol 22 (1) ◽  
pp. 32-34 ◽  
Author(s):  
M. Noguchi ◽  
T. Numata ◽  
Y. Mitani ◽  
T. Shino ◽  
S. Kawanaka ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Voltage Sensitivity ◽  
Back Gate ◽  
Fully Depleted

The Dependence of Carrier Distribution on Gate Capacitance of α-IGZO TFTs

2014 ◽  
Vol 598 ◽  
pp. 361-364 ◽  
Author(s):  
Chih Chieh Hsu ◽  
Chien Hsun Wu
Keyword(s):  
Threshold Voltage ◽  
Computer Aided Design ◽  
Gate Dielectric ◽  
Oxide Thin Film ◽  
High Electron ◽  
Indium Gallium Zinc Oxide ◽  
Gate Bias ◽  
Carrier Distribution ◽  
Fully Depleted ◽  
Gate Capacitance

The capacitance-voltage (C–V) characteristics of inverted staggered amorphous indium–gallium–zinc-oxide thin film transistors (α-IGZO TFTs) with various dimensions are investigated by physics-based technology computer aided design (TCAD) simulation. For gate bias lower than the threshold voltage of the TFT, the electrons in the channel region are nearly fully depleted. It causes that the total gate capacitance is determined by the overlap region of gate, α-IGZO, and source/drain metals. When the applied gate bias is higher than the threshold voltage, the high electron density channel with density of ~6 × 1017 cm-3 and thickness of ~3-4 nm is observed near the interface of α-IGZO and gate dielectric. It results that the total gate capacitance is dominated by the gate to channel overlap. Quantitative analysis of the carrier distribution and energy band structures are utilized to study the physical mechanism underlying the C–V characteristics of the α-IGZO TFTs.

New pixel circuits for controlling threshold voltage by back-gate bias voltage using crystalline oxide semiconductor FETs

2015 ◽  
Vol 24 (1) ◽  
pp. 35-43 ◽  
Author(s):  
Makoto Kaneyasu ◽  
Kouhei Toyotaka ◽  
Hideaki Shishido ◽  
Toshiyuki Isa ◽  
Shingo Eguchi ◽  
...  
Keyword(s):  
Bias Voltage ◽  
Threshold Voltage ◽  
Oxide Semiconductor ◽  
Gate Bias ◽  
Back Gate ◽  
Crystalline Oxide

57.3:Distinguished Paper: New Pixel Circuits for Controlling Threshold Voltage by Back-gate Bias Voltage using Crystalline Oxide Semiconductor FETs

2015 ◽  
Vol 46 (1) ◽  
pp. 857-860 ◽  
Author(s):  
Makoto Kaneyasu ◽  
Kouhei Toyotaka ◽  
Hideaki Shishido ◽  
Toshiyuki Isa ◽  
Shingo Eguchi ◽  
...  
Keyword(s):  
Bias Voltage ◽  
Threshold Voltage ◽  
Oxide Semiconductor ◽  
Gate Bias ◽  
Back Gate ◽  
Crystalline Oxide
Sign in / Sign up

Export Citation Format

Share Document