The Dependence of Carrier Distribution on Gate Capacitance of α-IGZO TFTs

The capacitance-voltage (C–V) characteristics of inverted staggered amorphous indium–gallium–zinc-oxide thin film transistors (α-IGZO TFTs) with various dimensions are investigated by physics-based technology computer aided design (TCAD) simulation. For gate bias lower than the threshold voltage of the TFT, the electrons in the channel region are nearly fully depleted. It causes that the total gate capacitance is determined by the overlap region of gate, α-IGZO, and source/drain metals. When the applied gate bias is higher than the threshold voltage, the high electron density channel with density of ~6 × 1017 cm-3 and thickness of ~3-4 nm is observed near the interface of α-IGZO and gate dielectric. It results that the total gate capacitance is dominated by the gate to channel overlap. Quantitative analysis of the carrier distribution and energy band structures are utilized to study the physical mechanism underlying the C–V characteristics of the α-IGZO TFTs.