Low temperature direct wafer to wafer bonding for 3D integration: Direct bonding, surface preparation, wafer-to-wafer alignment

Author(s):  
Gweltaz Gaudin ◽  
Gregory Riou ◽  
Didier Landru ◽  
Catherine Tempesta ◽  
Ionut Radu ◽  
...  
2010 ◽  
Vol 40 (1) ◽  
pp. 1-5 ◽  
Author(s):  
Michael J. Jackson ◽  
Li-Min Chen ◽  
Ankit Kumar ◽  
Yang Yang ◽  
Mark S. Goorsky

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 000836-000858 ◽  
Author(s):  
Sang Hwui Lee ◽  
Michael Khbeis

This paper reports on a successful 3D integration (3DI) of multi-purpose signal processor (MSP) chips with memory chips using die-to-wafer (D2W) and wafer-to-wafer (W2W) bonding technologies. 3D integration enables compact systems of commercial-off-the-shelf (COTS) parts with high functionality using a wafer-level process for better thinning process uniformity and high yield throughput. The3D system is comprised of commercial Flash memory bare die and MSP bare die. The bare die are face-down aligned to a 150mm diameter silicon handle wafer with alignment marks polished silicon surface. Unique features on the commercial die are detected and used for die registration using a flip-chip bonder with vision automation. An adhesive film between the die and silicon handle wafer are used for temporary bonding. After the die-to-wafer population and bonding, the die substrates are thinned at the wafer-level to a target of 60 microns for the memory die and 25 microns for the MSP die, respectively. The thinned memory die set is permanently transferred onto a 150mm diameter silicon carrier wafer using a low temperature silicon covalent wafer bonding. Following bonding, an adhesive film release process is used to separate the memory die set from the temporary handle wafer. The thinned MSP die on a second handle wafer are then aligned to the thinned memory die set using a wafer-to-wafer alignment tool, and bonded with thin-film polyimide in a high-yield, low temperature wafer bonding process, followed by the release process to separate the MSP die set from the handle wafer. Finally, the MSP/memory stack are electrically connected using a via-last through-silicon-via (TSV) process. One of the key considerations for COTS 3DI is to meet the back-end-of-line (BEOL) thermal budgets of 350–400 Celsius. Plasma-assisted preparation facilitates the reduction in thermal budget for silicon covalent bonding and is performed at 150 Celsius, followed by a long-term annealing process at 175 Celsius. Stacking of thinned die relies on low temperature polyimide bonding that is performed at 200 Celsius. Fluorine and oxygen based plasma surface activation process and CTE-matched polyimide bonding play a critical role in enabling the low temperature bonding for this 3D MSP/memory integration. The thinning and bonding processing details that are presented in this paper are essential for COTS 3DI but can also be applied to several low-profile multi-chip module and packaging applications.


2006 ◽  
Vol 914 ◽  
Author(s):  
Jian Yu ◽  
Richard L. Moore ◽  
Sang Hwui Lee ◽  
J. Jay McMahon ◽  
Jian-Qiang Lu ◽  
...  

AbstractBonding of pre-processed silicon wafers at back-end-of-the-line (BEOL) compatible conditions is one of the attractive approaches for three-dimensional (3D) integration. Among various technologies being evaluated, bonding of low temperature oxides (e.g., plasma-enhanced tetraethylorthosilicate (PETEOS)) is of great interest. In this work, we report low-temperature PETEOS-to-PETEOS wafer bonding, using a thin layer of titanium (Ti) as bonding intermediate. The bonding strength is evaluated qualitatively, while the bonding interface is examined by Auger electron spectroscopy (AES) and scanning electron microscopy (SEM). Preliminary results of PETEOS/Ti/PETEOS bonding on patterned wafers with single-level Cu damascene structures are also discussed.


2006 ◽  
Vol 970 ◽  
Author(s):  
Pei-I Wang ◽  
Tansel Karabacak ◽  
Jian Yu ◽  
Hui-Feng Li ◽  
Gopal G. Pethuraja ◽  
...  

ABSTRACTWafer bonding is an emerging technology for fabrication of complex three-dimensional (3D) structures; particularly it enables monolithic wafer-level 3D integration of high performance, multi-function microelectronic systems. For such a 3D integrated circuits, low-temperature wafer bonding is required to be compatible with the back-end-of-the-line processing conditions. Recently our investigation on surface melting characteristics of copper nanorod arrays showed that the threshold of the morphological changes of the nano-rod arrays occurs at a temperature significantly below the copper bulk melting point. With this unique property of the copper nanorod arrays, wafer bonding using copper nanorod arrays as a bonding intermediate layer was investigated at low temperatures (400 °C and lower). 200 mm Wafers, each with a copper nanorod array layer, were bonded at 200 – 400 °C and with a bonding down-force of 10 kN in a vacuum chamber. Bonding results were evaluated by razor blade test, mechanical grinding and polishing, and cross-section imaging using a focus ion beam/scanning electron microscope (FIB/SEM). The FIB/SEM images show that the copper nanorod arrays fused together accompanying by a grain growth at a bonding temperature of as low as 200 °C. A dense copper bonding layer was achieved at 400 °C where copper grains grew throughout the copper structure and the original bonding interface was eliminated. The sintering of such nanostructures depends not only on their feature size, but also significantly influenced by the bonding pressure. These two factors both contribute to the mass transport in the nanostructure, leading to the formation of a dense bonding layer.


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