Low Temperature Copper-Nanorod Bonding for 3D Integration

2006 ◽  
Vol 970 ◽  
Author(s):  
Pei-I Wang ◽  
Tansel Karabacak ◽  
Jian Yu ◽  
Hui-Feng Li ◽  
Gopal G. Pethuraja ◽  
...  
Keyword(s):  
Low Temperature ◽  
Wafer Bonding ◽  
Morphological Changes ◽  
Ion Beam ◽  
Bonding Temperature ◽  
Bonding Layer ◽  
Nanorod Arrays ◽  
3D Integration ◽  
Sem Images ◽  
Bonding Pressure

ABSTRACTWafer bonding is an emerging technology for fabrication of complex three-dimensional (3D) structures; particularly it enables monolithic wafer-level 3D integration of high performance, multi-function microelectronic systems. For such a 3D integrated circuits, low-temperature wafer bonding is required to be compatible with the back-end-of-the-line processing conditions. Recently our investigation on surface melting characteristics of copper nanorod arrays showed that the threshold of the morphological changes of the nano-rod arrays occurs at a temperature significantly below the copper bulk melting point. With this unique property of the copper nanorod arrays, wafer bonding using copper nanorod arrays as a bonding intermediate layer was investigated at low temperatures (400 °C and lower). 200 mm Wafers, each with a copper nanorod array layer, were bonded at 200 – 400 °C and with a bonding down-force of 10 kN in a vacuum chamber. Bonding results were evaluated by razor blade test, mechanical grinding and polishing, and cross-section imaging using a focus ion beam/scanning electron microscope (FIB/SEM). The FIB/SEM images show that the copper nanorod arrays fused together accompanying by a grain growth at a bonding temperature of as low as 200 °C. A dense copper bonding layer was achieved at 400 °C where copper grains grew throughout the copper structure and the original bonding interface was eliminated. The sintering of such nanostructures depends not only on their feature size, but also significantly influenced by the bonding pressure. These two factors both contribute to the mass transport in the nanostructure, leading to the formation of a dense bonding layer.

Low Temperature Bonding via Copper Nanowires for 3D Integrated Circuits

2010 ◽  
Vol 1249 ◽  
Author(s):  
Shu Rong Chun ◽  
Wardhana Aji Sasangka ◽  
Chee Lip Gan ◽  
Hui Cai ◽  
Chee Mang Ng
Keyword(s):  
Shear Strength ◽  
Low Temperature ◽  
Integrated Circuits ◽  
Ion Beam ◽  
Bonding Temperature ◽  
Copper Nanowires ◽  
Aao Template ◽  
Sem Images ◽  
3D Integrated Circuits ◽  
Low Temperature Bonding

AbstractLow temperature bonding is desired for compatibility with back-end-of-line processing (BEOL) conditions in order not to affect the three dimensional (3D) Integrated Circuits (IC) device performance. In this paper, the aim is to demonstrate that thermocompression bonding temperature can be lowered by changing the copper (Cu) film with Cu nanowires fabricated via electrodeposition through anodized aluminum oxide (AAO) template. A comparison was done between film-to-film (Film-Film) and nanowires-to-nanowires (NWs-NWs) bonding in terms of microstructure and shear strength. Cross-sectional images captured by Focused Ion Beam (FIB) revealed good interface between NWs-NWs bonding as the nanowires had fused together. Scanning Electron Microscope (SEM) images of samples after shear test also demonstrated that there is good adhesion between the bonding layers. Results from shear tests showed an increase in shear strength of NWs-NWs bonding as compared to that of Film-Film bonding at 200 °C. In addition, NWs-NWs bonding at 300 °C achieved higher shear strength than at 200 °C. In this study, it has been shown that copper nanowires fabricated via electrodeposition through porous AAO template can be a potential method to form a bonding intermediate layer for 3D ICs.

Sol-Gel Coating Facilitating Si-to-Si Wafer Bonding at Low Temperature

2005 ◽  
Author(s):  
J. Wei ◽  
S. S. Deng ◽  
C. M. Tan
Keyword(s):  
Low Temperature ◽  
Bond Strength ◽  
Wafer Bonding ◽  
Intermediate Layer ◽  
Bonding Temperature ◽  
Sol Gel ◽  
Bond Quality ◽  
Bubble Generation ◽  
High Bond ◽  
High Bond Strength

Silicon-to-silicon wafer bonding by sol-gel intermediate layer has been performed using acid-catalyzed tetraethylthosilicate-ethanol-water sol solution. High bond strength near to the fracture strength of bulk silicon is obtained at low temperature, for example 100°C. However, The bond efficiency and bond strength of this intermediate layer bonding sharply decrease when the bonding temperature increases to elevated temperature, such as 300 °C. The degradation of bond quality is found to be related to the decomposition of residual organic species at elevated bonding temperature. The bubble generation and the mechanism of the high bond strength at low temperature are exploited.

Low Temperature Wafer Level Bonding Using Benzocyclobutene Adhesive Polymers

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 1-24
Author(s):  
Michael Gallagher ◽  
Jong-Uk Kim ◽  
Eric Huenger ◽  
Kai Zoschke ◽  
Christina Lopper ◽  
...  
Keyword(s):  
Low Temperature ◽  
Wafer Bonding ◽  
Flip Chip ◽  
Bonding Temperature ◽  
Bonding Process ◽  
Curing Temperature ◽  
Wafer Level ◽  
Mechanical Adhesion ◽  
3D Stacking ◽  
Dry Etch

3D stacking, one of the 3D integration technologies using through silicon vias (TSVs), is considered as a desirable 3D solution due to its cost effectiveness and matured technical background. For successful 3D stacking, precisely controlled bonding of the two substrates is necessary, so that various methods and materials have been developed over the last decade. Wafer bonding using polymeric adhesives has advantages. Surface roughness, which is critical in direct bonding and metal-to-metal bonding, is not a significant issue, as the organic adhesive can smooth out the unevenness during bonding process. Moreover, bonding of good quality can be obtained using relatively low bonding pressure and low bonding temperature. Benzocyclobutene (BCB) polymers have been commonly used as bonding adhesives due to their relatively low curing temperature (~250 °C), very low water uptake (<0.2%), excellent planarizing capability, and good affinity to Cu metal lines. In this study, we present wafer bonding with BCB at various conditions. In particular, bonding experiments are performed at low temperature range (180 °C ~ 210 °C), which results in partially cured state. In order to examine the effectiveness of the low temperature process, the mechanical (adhesion) strength and dimensional changes are measured after bonding, and compared with the values of the fully cured state. Two different BCB polymers, dry-etch type and photo type, are examined. Dry etch BCB is proper for full-area bonding, as it has low degree of cure and therefore less viscosity. Photo-BCB has advantages when a pattern (frame or via open) is to be structured on the film, since it is photoimageable (negative tone), and its moderate viscosity enables the film to sustain the patterns during the wafer bonding process. The effect of edge beads at the wafer rim area and the soft cure (before bonding) conditions on the bonding quality are also studied. Alan/Rey ok move from Flip Chip and Wafer Level Packaging 1-6-12.

Low Temperature Direct Cu-Cu Immersion Bonding for 3D Integration

2009 ◽  
Vol 1156 ◽  
Author(s):  
Rahul Agarwal ◽  
Wouter Ruythooren
Keyword(s):  
Citric Acid ◽  
Low Temperature ◽  
Bonding Temperature ◽  
Atmospheric Condition ◽  
High Strength ◽  
Bonding Process ◽  
3D Integration ◽  
Temperature And Pressure ◽  
Low Temperature Bonding

AbstractHigh yielding and high strength Cu-Cu thermo-compression bonds have been obtained at temperatures as low as 175°C. Plated Cu bumps are used for bonding, without any surface planarization step or plasma treatment, and bonding is performed at atmospheric condition. In this work the 25μm diameter bumps are used at a bump pitch of 100μm and 40μm. Low temperature bonding is achieved by using immersion bonding in citric acid. Citric acid provides in-situ cleaning of the Cu surface during the bonding process. The daisy chain electrical bonding yield ranges from 84%-100% depending on the bonding temperature and pressure.

Studies of Temperature and Pressure Dependence in Thermocompression Gold Joints

2005 ◽  
Author(s):  
X. F. Ang ◽  
G. G. Zhang ◽  
J. Wei ◽  
Z. Chen ◽  
C. C. Wong
Keyword(s):  
Shear Strength ◽  
Critical Temperature ◽  
Pressure Dependence ◽  
Bonding Temperature ◽  
Interfacial Stress ◽  
3D Integration ◽  
Bonding Pressure ◽  
Barrier Films ◽  
Linear Rise ◽  
Temperature And Pressure

Low temperature interconnection is a critical component of 3D integration and packaging technology. In this study, we investigate the characteristics of thermocompression metal bonding using gold stud bumps formed on Si die in the temperature range of 100-300 °C and the pressure range of 200–600 g/bump. We observed a critical bonding temperature below which bonding did not occur and above which shear strength improves linearly with bonding temperature. This critical temperature can be interpreted to be the onset of the break-up of organic barrier films while the linear rise in shear strength can be attributed to the increase in the true bonded area. Above this critical temperature, the tensile strength of the Au-Au bond exhibits a maximum with increasing bonding pressure. This can be related to the pressure dependence of the interfacial stress distribution and its effect on unbonded radius, r. SEM fractographs of the failed surfaces suggest a combination of cohesive and adhesive failures along the bonded interface.

Commercial-off-the-Shelf (COTS) 3D Integration using Low Temperature Wafer Bonding

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 000836-000858 ◽  
Author(s):  
Sang Hwui Lee ◽  
Michael Khbeis
Keyword(s):  
Low Temperature ◽  
Wafer Bonding ◽  
High Yield ◽  
Activation Process ◽  
Wafer Level ◽  
3D Integration ◽  
Release Process ◽  
Adhesive Film ◽  
Die Set ◽  
Commercial Off The Shelf

This paper reports on a successful 3D integration (3DI) of multi-purpose signal processor (MSP) chips with memory chips using die-to-wafer (D2W) and wafer-to-wafer (W2W) bonding technologies. 3D integration enables compact systems of commercial-off-the-shelf (COTS) parts with high functionality using a wafer-level process for better thinning process uniformity and high yield throughput. The3D system is comprised of commercial Flash memory bare die and MSP bare die. The bare die are face-down aligned to a 150mm diameter silicon handle wafer with alignment marks polished silicon surface. Unique features on the commercial die are detected and used for die registration using a flip-chip bonder with vision automation. An adhesive film between the die and silicon handle wafer are used for temporary bonding. After the die-to-wafer population and bonding, the die substrates are thinned at the wafer-level to a target of 60 microns for the memory die and 25 microns for the MSP die, respectively. The thinned memory die set is permanently transferred onto a 150mm diameter silicon carrier wafer using a low temperature silicon covalent wafer bonding. Following bonding, an adhesive film release process is used to separate the memory die set from the temporary handle wafer. The thinned MSP die on a second handle wafer are then aligned to the thinned memory die set using a wafer-to-wafer alignment tool, and bonded with thin-film polyimide in a high-yield, low temperature wafer bonding process, followed by the release process to separate the MSP die set from the handle wafer. Finally, the MSP/memory stack are electrically connected using a via-last through-silicon-via (TSV) process. One of the key considerations for COTS 3DI is to meet the back-end-of-line (BEOL) thermal budgets of 350–400 Celsius. Plasma-assisted preparation facilitates the reduction in thermal budget for silicon covalent bonding and is performed at 150 Celsius, followed by a long-term annealing process at 175 Celsius. Stacking of thinned die relies on low temperature polyimide bonding that is performed at 200 Celsius. Fluorine and oxygen based plasma surface activation process and CTE-matched polyimide bonding play a critical role in enabling the low temperature bonding for this 3D MSP/memory integration. The thinning and bonding processing details that are presented in this paper are essential for COTS 3DI but can also be applied to several low-profile multi-chip module and packaging applications.

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