Effects of rapid thermal processing on the current gain and emitter resistance of polysilicon emitter bipolar transistors

1991 ◽  
Vol 12 (1) ◽  
pp. 10-12 ◽  
Author(s):  
L.M. Castaner ◽  
P. Ashburn ◽  
G.R. Wolstenholme
1989 ◽  
Vol 146 ◽  
Author(s):  
Fred Ruddell ◽  
Colin Parkes ◽  
B Mervyn Armstrong ◽  
Harold S Gamble

ABSTRACTThis paper describes a LPCVD reactor which was developed for multiple sequential in-situ processing. The system is capable of rapid thermal processing in the presence of plasma stimulation and has been used for native oxide removal, plasma oxidation and silicon deposition. Polysilicon layers produced by the system are incorporated into N-P-N polysilicon emitter bipolar transistors. These devices fabricated using a sequential in-situ plasma clean-polysilicon deposition schedule exhibited uniform gains limited to that of long single crystal emitters. Devices with either plasma grown or native oxide layers below the polysilicon exhibited much higher gains. The suitability of the system for sequential and limited reaction processing has been established.


1996 ◽  
Vol 429 ◽  
Author(s):  
W. E. Leitz ◽  
G. Modi ◽  
N. Parekh ◽  
E. Sabin ◽  
R. V. Taylor

AbstractRapid Thermal Processing (RTP) has sometimes been used to increase bipolar NPN Beta (Hfe, or current gain) for a polysilicon emitter BICMOS process. It has been demonstrated that Beta may be increased by 20%, compared to normal non-RTP process values, by the addition of an RTP cycle after the final high temperature furnace step. In our work it was found that emitter-base reverse bias degrades Beta much more severely for a process which uses RTP, than for a non-RTP process. In this paper we will report on the electrical performance effects of RTP on a variety of process parameters. The reliability effects on NPN Beta degradation lifetime, and NMOS reliability effects will be discussed as well.


1994 ◽  
Vol 11 (3) ◽  
pp. 277-283
Author(s):  
Huang Liuxing ◽  
Wei Tongli ◽  
Zheng Jiang ◽  
Cao Juncheng

1987 ◽  
Vol 92 ◽  
Author(s):  
R. S. Hockett

ABSTRACTRapid Thermal Processing is being evaluated in the IC industry as a way to meet the thermal budget requirements of reduced scaling in high performance Si IC's. As scaling is reduced and alternative processing is used, the study of low level interfacial impurities is expected to become more important. An example is presented here for the redistribution of interfacial impurities under RTP for polysilicon capped silicon similar to that proposed for shallow junction bipolar transistors.


1992 ◽  
Vol 260 ◽  
Author(s):  
T. S. Kalkur ◽  
P. D. Wright ◽  
S. K. Ko ◽  
Y. C. Lu ◽  
L. Casas ◽  
...  

ABSTRACTTi/Pt metallization was used to form contacts on both n+-InAs emitter cap and p+ base layers of heterojunction bipolar transistors (HBTs). The as-deposited contacts were found to be ohmic for both the base and emitter cap layers. Rapid thermal processing of the contact metallizations was performed in the temperature range of 3 00–500 C for 30 seconds. Minimum contact resistivities of l×10-6 ohm-cm2 for the base and 3×l0-7 ohm-cm2 for the emitter layer were achieved. The influence of heat treatment on contact morphology was also examined.


1992 ◽  
Vol 39 (6) ◽  
pp. 1392-1397 ◽  
Author(s):  
A. Nouailhat ◽  
G. Giroult-Matlakowski ◽  
A. Marty ◽  
N. Degors ◽  
M.-D. Bruni ◽  
...  

1996 ◽  
Vol 43 (8) ◽  
pp. 1281-1285 ◽  
Author(s):  
T. Shiba ◽  
M. Kondo ◽  
T. Uchino ◽  
H. Murakoshi ◽  
Y. Tamaki

1987 ◽  
Vol 92 ◽  
Author(s):  
A. Kermani ◽  
F. Van Gieson ◽  
S. Litwin ◽  
R. Sullivan ◽  
T. J. DeBolske ◽  
...  

ABSTRACTThe activation of ion implanted emitters for two types of NPN bipolar junction transistors ( BJT ) by rapid thermal processing (RTP) was evaluated. The dopant profiles and the resultant junction depths were measured for various thermal cycles, using spreading resistance profile technique. The electrical characteristics of the transistors were then determined and compared to the standard furnace processes. The common emitter current gain values, hFE, for arsenic emitters were low and phosphorous emitters exhibited improved or comparable betas. The breakdown voltages in common emitter configuration, BV,CEO, BVcEs and BVEBO were comparable or better than the furnace annealed samples and no evidence of transistor leakage was observed.


1989 ◽  
Vol 146 ◽  
Author(s):  
J. E. Urner ◽  
C. I. Drowley ◽  
P. Vande Voorde ◽  
A. Kermani

ABSTRACTThe development of next-generation high-speed bipolar devices depends critically on reproducible shallow dopant profiles, with base and emitter widths considerably less than 1000 Angstroms. Sequential diffusion of boron and arsenic from implanted polysilicon is a promising means of producing such shallow emitter-base profiles. The restricted thermal budget required to reproducibly form such shallow junctions severely limits the use of conventional furnaces. We report the formation of extremely shallow emitter-base profiles using rapid thermal processing (RTP) in a double-diffused polysilicon emitter process. Polysilicon was implanted with various doses of BF2 and subjected to a conventional furnace anneal at 900ºC. This process was followed by As implantation and furnace anneal at 900ºC or RTP at 10500C or 1100ºC. A range of emitter-base profiles was generated with emitter and base widths ranging from 350-800A. Emitter-base profiles were measured using low-energy Secondary Ion Mass Spectrometry (SIMS), after removal of the polysilicon to improve depth resolution. Deconvolution of the instrumental broadening function allowed extraction of base and emitter widths as well as the boron concentration in the base. Variation of the profiles is discussed as a function of anneal times and implant dose. Modified SUPREM III parameters are obtained for diffusivities under these RTP conditions. The implications for high speed bipolar device fabrication will be presented.


Sign in / Sign up

Export Citation Format

Share Document