The Redistribution of Impurities Under RTP for Polysilicon Capped Silicon

1987 ◽  
Vol 92 ◽  
Author(s):  
R. S. Hockett
Keyword(s):  
Thermal Processing ◽  
High Performance ◽  
Rapid Thermal Processing ◽  
Bipolar Transistors ◽  
Thermal Budget ◽  
Shallow Junction ◽  
Low Level ◽  
Alternative Processing

ABSTRACTRapid Thermal Processing is being evaluated in the IC industry as a way to meet the thermal budget requirements of reduced scaling in high performance Si IC's. As scaling is reduced and alternative processing is used, the study of low level interfacial impurities is expected to become more important. An example is presented here for the redistribution of interfacial impurities under RTP for polysilicon capped silicon similar to that proposed for shallow junction bipolar transistors.

Beyond Thermal Budget: Using D · t In Kinetic Optimization Of RTP

1998 ◽  
Vol 525 ◽  
Author(s):  
R. Ditchfield ◽  
E. G. Seebauer
Keyword(s):  
Thermal Processing ◽  
Program Design ◽  
Rapid Thermal Processing ◽  
Dopant Diffusion ◽  
Thermal Budget ◽  
Microelectronic Fabrication ◽  
Kinetic Effects ◽  
Rigorous Method

ABSTRACTRapid thermal processing (RTP) has found continually increasing use for oxidation, silicidation, CVD, and other steps in microelectronic fabrication. Kinetic effects in rapid thermal processing (RTP) are often assessed using the concept of thermal budget, with the idea that low thermal budgets should minimize dopant diffusion and interface degradation. Some definitions of budget employ the product of temperature and time (T-t). In previous work, we have shown that this definition for budget often leads to qualitatively incorrect conclusions regarding heating program design. However, other definitions of budget employ the product of diffusivity and time (D-t), where the diffusivity describes unwanted diffusion or interface degradation. Here we show that minimization of D-t by itself is insufficient to kinetically optimize a heating program; account must be taken of the relative rates of the desired and undesired phenomena. We present a straightforward but rigorous method for doing so.

Low temperature shallow junction formation using vacuum ultraviolet photons during rapid thermal processing

1997 ◽  
Vol 70 (13) ◽  
pp. 1700-1702 ◽  
Author(s):  
R. Singh ◽  
K. C. Cherukuri ◽  
L. Vedula ◽  
A. Rohatgi ◽  
S. Narayanan
Keyword(s):  
Low Temperature ◽  
Thermal Processing ◽  
Vacuum Ultraviolet ◽  
Rapid Thermal Processing ◽  
Shallow Junction ◽  
Junction Formation ◽  
Ultraviolet Photons

Polysilicon Emitter Transistors Manufactured using a Novel Limited Reaction Processing System

1989 ◽  
Vol 146 ◽  
Author(s):  
Fred Ruddell ◽  
Colin Parkes ◽  
B Mervyn Armstrong ◽  
Harold S Gamble
Keyword(s):  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Processing System ◽  
Bipolar Transistors ◽  
Native Oxide ◽  
Plasma Oxidation ◽  
Oxide Removal ◽  
Polysilicon Emitter ◽  
Reaction Processing

ABSTRACTThis paper describes a LPCVD reactor which was developed for multiple sequential in-situ processing. The system is capable of rapid thermal processing in the presence of plasma stimulation and has been used for native oxide removal, plasma oxidation and silicon deposition. Polysilicon layers produced by the system are incorporated into N-P-N polysilicon emitter bipolar transistors. These devices fabricated using a sequential in-situ plasma clean-polysilicon deposition schedule exhibited uniform gains limited to that of long single crystal emitters. Devices with either plasma grown or native oxide layers below the polysilicon exhibited much higher gains. The suitability of the system for sequential and limited reaction processing has been established.

Rapid Thermal Processing and The Quest for Ultra Shallow Boron Junctions

1986 ◽  
Vol 71 ◽  
Author(s):  
Tom Sedgwick
Keyword(s):  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Attractive Potential ◽  
High Activation ◽  
Shallow Junction ◽  
Enhanced Diffusion ◽  
Transient Enhanced Diffusion ◽  
Diffusion Effects ◽  
Junction Formation ◽  
Short Time

AbstractRapid Thermal Processing (RTP) can minimize processing time and therefore minimize dopant motion during annealing of ion implanted junctions. In spite of the advantage of short time annealing using RTP, the formation of shallow B junctions is thwarted by channeling, transient enhanced diffusion and concentration enhanced diffusion effects all of which lead to deeper B profiles. Channeling and transient enhanced diffusion can be avoided by preamorphizing the silicon before the B implant. However, defects at the original amorphous/crystal boundary persist after annealing. Very low energy B implantation can lead to very shallow dopant profiles and in spite of channeling effects, offers an attractive potential shallow junction technology. In all of the shallow junction formation techniques RTP is required to achieve both high activation of the implanted species and minimal diffusion of the implanted dopant.

In-Situ Fabrication and Process Control Techniques in Rapid Thermal Processing

1991 ◽  
Vol 224 ◽  
Author(s):  
Mehrdad M. Moslehi ◽  
John Kuehne ◽  
Richard Yeakley ◽  
Lino Velo ◽  
Habib Najm ◽  
...  
Keyword(s):  
Process Control ◽  
Thermal Processing ◽  
Polycrystalline Silicon ◽  
High Performance ◽  
Rapid Thermal Processing ◽  
Control Techniques ◽  
In Situ Fabrication ◽  
Concurrent Use ◽  
Process Uniformity

AbstractAdvanced rapid thermal processing (RTP) equipment and sensors have been developed for in-situ fabrication of semiconductor devices. High-performance multi-zone lamp modules have been applied to various processes including rapid thermal oxidation (RTO), chemicalvapor deposition (CVD) of tungsten and amorphous/polycrystalline silicon, silicide formation, as well as high-temperature rapid thermal annealing (RTA). Concurrent use of multizone lamps and multi-point temperature sensors allows real-time wafer temperature control and process uniformity optimization. Specific experimental results will be presented on the multi-zone lamp modules, in-situ process control sensors, and single-wafer fabrication processes.

Understanding the Impact of Batch vs. Single Wafer in Thermal Processing Using Cost of Ownership Analysis

1997 ◽  
Vol 470 ◽  
Author(s):  
S. Hossain-Pas ◽  
M. F. Pas
Keyword(s):  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Chemical Vapor ◽  
Financial Impact ◽  
Enabling Technology ◽  
Thermal Budget ◽  
Thermal Chemical Vapor Deposition ◽  
Cost Of Ownership ◽  
Technology Nodes ◽  
The Impact

IntroductionBatch thermal processing satisfies device requirements for 0.5μm and larger technology nodes for silicon semiconductor manufacturing and continues to satisfy these requirements as feature sizes decrease beyond 0.5μm to 0.35μm. At the transition from 0.35μm to 0.25μm, source/drain (S/D) anneal, TiSi form, and TiSi anneal require rapid thermal processing (RTP) because of improvements in thermal budget, lateral dopant diffusion, and in silicidation, with RTP. RTP and rapid thermal chemical vapor deposition (RTCVD) become enabling technology for devices at 0.25μm and smaller technology nodes.A cost of ownership (CoO) analysis provides a comparison between the financial impact of alternatives and helps in determining the lowest cost answer for that process, assuming all other process parameters can be met equally by all alternatives. This report analyzes primary cost drivers, their importance within each analysis, and potential for improvements which may cause a significant change in CoO values at 200mm.

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