Synthesis of CMOS Domino Circuits for Charge Sharing Alleviation

2009 ◽  
Keyword(s):  
Charge Sharing ◽  
Domino Circuits

Low Power Wide Fan-in Domino OR Gate Using CN-MOSFETs

2020 ◽  
Vol 10 (1) ◽  
pp. 55-62
Author(s):  
Deepika Bansal ◽  
Bal Chand Nagar ◽  
Brahamdeo Prasad Singh ◽  
Ajay Kumar
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Dynamic Logic ◽  
Clock Frequency ◽  
Charge Sharing ◽  
Benchmark Circuit ◽  
Domino Circuit ◽  
Power Delay Product ◽  
Domino Circuits ◽  
Or Gate

Background & Objective: In this paper, a modified pseudo domino configuration has been proposed to improve the leakage power consumption and Power Delay Product (PDP) of dynamic logic using Carbon Nanotube MOSFETs (CN-MOSFETs). The simulations for proposed and published domino circuits are verified by using Synopsys HSPICE simulator with 32nm CN-MOSFET technology which is provided by Stanford. Methods: The simulation results of the proposed technique are validated for improvement of wide fan-in domino OR gate as a benchmark circuit at 500 MHz clock frequency. Results: The proposed configuration is suitable for cascading of the high performance wide fan-in circuits without any charge sharing. Conclusion: The performance analysis of 8-input OR gate demonstrate that the proposed circuit provides lower static and dynamic power consumption up to 62 and 40% respectively, and PDP improvement is 60% as compared to standard domino circuit.

Charge-sharing alleviation and detection for CMOS domino circuits

2001 ◽  
Vol 20 (2) ◽  
pp. 266-280 ◽  
Author(s):  
Shih-Chieh Chang ◽  
Ching-Hwa Cheng ◽  
Wen-Ben Jone ◽  
Shin-De Lee ◽  
Jinn-Shyan Wang
Keyword(s):  
Charge Sharing ◽  
Domino Circuits

scholarly journals Stack Contention-alleviated Precharge Keeper for Pseudo Domino Logic

2017 ◽  
Vol 6 (2) ◽  
pp. 122-132
Author(s):  
Deepika Bansal ◽  
Brahmadeo Prasad Singh ◽  
Ajay Kumar
Keyword(s):  
Performance Improvement ◽  
Power Dissipation ◽  
Logic Gates ◽  
Logic Circuits ◽  
Charge Sharing ◽  
Domino Logic ◽  
Dynamic Circuits ◽  
Low Power Dissipation ◽  
High System ◽  
Domino Circuits

The dynamic circuits are supposed to offer superior speed and low power dissipation over static CMOS circuits. The domino logic circuits are used for high system performance but suffer from the precharge pulse degradation. This article provides different design topologies on the domino circuits to overcome the charge sharing and charge leakage with reference to the power dissipation and delay. The precharge keeper circuit has been proposed such that the keeper transistors also work as the precharge transistors to realize multiple output function. The performance improvement of the circuit’s analysis have been done for adders and logic gates using HSPICE tool. The proposed keeper techniques reveal lower power dissipation and lesser delay over the standard keeper circuit with less transistor count for different process variation.

Low-speed scan testing of charge-sharing faults for CMOS domino circuits

2000 ◽  
Vol 36 (20) ◽  
pp. 1684
Author(s):  
C.H. Cheng ◽  
W.B. Jone ◽  
S.C. Chang ◽  
J.S. Wang
Keyword(s):  
Charge Sharing ◽  
Scan Testing ◽  
Low Speed ◽  
Domino Circuits

scholarly journals Charge Sharing and Charge Loss in High-Flux Capable Pixelated CdZnTe Detectors

Sensors ◽  
2021 ◽  
Vol 21 (9) ◽  
pp. 3260
Author(s):  
Kjell A. L. Koch-Mehrin ◽  
Sarah L. Bugby ◽  
John E. Lees ◽  
Matthew C. Veale ◽  
Matthew D. Wilson
Keyword(s):  
Carrier Transport ◽  
Hole Transport ◽  
Uniform Electric Field ◽  
Photon Flux ◽  
High Flux ◽  
Charge Sharing ◽  
Cdte Detector ◽  
Charge Loss ◽  
Cdznte Detectors ◽  
Detector Model

Cadmium zinc telluride (CdZnTe) detectors are known to suffer from polarization effects under high photon flux due to poor hole transport in the crystal material. This has led to the development of a high-flux capable CdZnTe material (HF-CdZnTe). Detectors with the HF-CdZnTe material have shown promising results at mitigating the onset of the polarization phenomenon, likely linked to improved crystal quality and hole carrier transport. Better hole transport will have an impact on charge collection, particularly in pixelated detector designs and thick sensors (>1 mm). In this paper, the presence of charge sharing and the magnitude of charge loss were calculated for a 2 mm thick pixelated HF-CdZnTe detector with 250 μm pixel pitch and 25 μm pixel gaps, bonded to the STFC HEXITEC ASIC. Results are compared with a CdTe detector as a reference point and supported with simulations from a Monte-Carlo detector model. Charge sharing events showed minimal charge loss in the HF-CdZnTe, resulting in a spectral resolution of 1.63 ± 0.08 keV Full Width at Half Maximum (FWHM) for bipixel charge sharing events at 59.5 keV. Depth of interaction effects were shown to influence charge loss in shared events. The performance is discussed in relation to the improved hole transport of HF-CdZnTe and comparison with simulated results provided evidence of a uniform electric field.

scholarly journals A 1T2C FeCAP-Based In-Situ Bitwise X(N)OR Logic Operation with Two-Step Write-Back Circuit for Accelerating Compute-In-Memory

Micromachines ◽  
2021 ◽  
Vol 12 (4) ◽  
pp. 385
Author(s):  
Qiao Wang ◽  
Donglin Zhang ◽  
Yulin Zhao ◽  
Chao Liu ◽  
Qiao Hu ◽  
...  
Keyword(s):  
Nonvolatile Memory ◽  
High Reliability ◽  
Charge Sharing ◽  
Operation Speed ◽  
Sharing Function ◽  
Logic Operations ◽  
A Charge ◽  
Process Compatibility ◽  
Ferroelectric Capacitors

Ferroelectric capacitors (FeCAPs) with high process compatibility, high reliability, ultra-low programming current and fast operation speed are promising candidates to traditional volatile and nonvolatile memory. In addition, they have great potential in the fields of storage, computing, and memory logic. Nevertheless, effective methods to realize logic and memory in FeCAP devices are still lacking. This study proposes a 1T2C FeCAP-based in situ bitwise X(N)OR logic based on a charge-sharing function. First, using the 1T2C structure and a two-step write-back circuit, the nondestructive reading is realized with less complexity than the previous work. Second, a method of two-line activation is used during the operation of X(N)OR. The verification results show that the speed, area and power consumption of the proposed 1T2C FeCAP-based bitwise logic operations are significantly improved.

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