scholarly journals Characterization of high-resistivity polycrystalline silicon substrates for wafer-level packaging and integration of RF passives

Author(s):  
M. Bartek ◽  
A. Polyakov ◽  
S.M. Sinaga ◽  
P.M. Mendes ◽  
J.H. Correia ◽  
...  
2005 ◽  
Vol 41 (2) ◽  
pp. 100 ◽  
Author(s):  
A. Polyakov ◽  
S. Sinaga ◽  
P.M. Mendes ◽  
M. Bartek ◽  
J.H. Correia ◽  
...  

2019 ◽  
Vol 142 (1) ◽  
Author(s):  
Hsien-Chie Cheng ◽  
Yan-Cheng Liu

Abstract This study presents a comprehensive assessment of the process-induced warpage of molded wafer for chip-first, face-down fan-out wafer-level packaging (FOWLP) during the fan-out fabrication process. A process-dependent simulation methodology is introduced, which integrates nonlinear finite element (FE) analysis and element death-birth technique. The effects of the cure-dependent volumetric shrinkage, geometric nonlinearity, and gravity loading on the process-induced warpage are examined. The study starts from experimental characterization of the temperature-dependent material properties of the applied liquid type epoxy molding compound (EMC) system through dynamic mechanical analysis (DMA) and thermal mechanical analysis. Furthermore, its cure state (heat of reaction and degree of cure (DOC)) during the compression molding process (CMP) is measured by differential scanning calorimetry (DSC) tests. Besides, the cure dependent-volumetric (chemical) shrinkages of the EMC system after the in-mold cure (IMC) and postmold cure (PMC) are experimentally determined by which the volumetric shrinkage at the gelation point is predicted through a linear extrapolation approach. To demonstrate the effectiveness of the proposed theoretical model, the prediction results are compared against the inline warpage measurement data. One possible cause of the asymmetric/nonaxisymmetric warpage is also addressed. Finally, the influences of some geometric dimensions on the warpage of the molded wafer are identified through parametric analysis.


2017 ◽  
Vol 2017 (1) ◽  
pp. 000258-000262
Author(s):  
Bart Vereecke ◽  
Philippe Soussan ◽  
Jian Zhu

Abstract Very small RF modules can be realized through heterogenous integration of GaAs MMIC (monolithic microwave integrated circuit) onto a low loss Si sub-mount, with high density routing lines realized by advanced patterning. In this paper we investigate how to integrate MMIC active devices on GaAs with the RF passives produced on an interposer, using Si wafer process technology. High resistive Silicon substrates are required to minimize RF losses. The interposer is thinned below 100 μm to reveal Cu TSVs from the back of the interposer, while the front side is covered entirely with a silicon capping wafer for shielding the device. We compare different wafer level packaging approaches for producing the low RF-loss interposers, and populating them using die-to-die (D2D) or die-to-wafer (D2W) bonding of the MMIC components, followed by wafer level encapsulation. Two D2W approaches are compared, in the first approach the D2W mounting and the encapsulation happens before the Si interposer is thinned for TSV reveal. To avoid damage during thinning of the wafer, thicker substrates with deeper TSV of 150 μm or more are required. In a second approach, the thinning of the interposer is done prior to the mounting. Initial electrical data showed that the approach yielded proper RF performance, but further yield optimization is required.


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