B-ternary logic and evaluation of binary logic programs

2003 ◽  
Author(s):  
Z. Huang ◽  
D.C. Rine
Keyword(s):  
Logic Programs ◽  
Ternary Logic ◽  
Binary Logic

A Universal Method for Designing Multi-Digit Ternary to Binary Converter Using CNTFET

2020 ◽  
Vol 29 (12) ◽  
pp. 2050196 ◽  
Author(s):  
Maryam Shahangian ◽  
Seied Ali Hosseini ◽  
Reza Faghih Mirzaee
Keyword(s):  
Threshold Voltage ◽  
High Efficiency ◽  
Field Effect Transistors ◽  
Block Diagram ◽  
Universal Method ◽  
Ternary Logic ◽  
Chip Area ◽  
Binary Logic ◽  
Multiple Valued Logic ◽  
Essential Components

Ternary logic can reduce the number of interconnections, chip area and power dissipation. In addition, one of the important features of carbon nanotube field effect transistors (CNTFETs) is the capability of adjusting threshold voltage. As a result, the design complexity of ternary circuits can be decreased. The structure of a mixed radix system which is based on multi-valued and binary logic is more appropriate compared to only multiple-valued logic (MVL). Therefore, ternary-to-binary and binary-to-ternary converters are the essential components for the ternary signaling on the bus and the binary logic processing circuits. It is also important for the creation of compatibility between the binary and ternary logic. This study is about a multi-digit binary-to-ternary converter by using CNTFET. At first, the algorithm used for the multi-digit conversion from ternary to binary logic is addressed in this paper. Then, the paper proposes a block diagram suitable for designing the multi-digit ternary-to-binary converter. Some new gates including One-Active Gate and Two-Active Gate, as well as two types of binary half-and full-adders, are designed for the purpose of implementing the proposed block diagram. This is done by adjusting the proper threshold voltage for CNTFETs. The proposed algorithm can also be applied to any desired number of bits. The proper operation and high efficiency of the proposed converter are confirmed by HSPICE simulation results and 32[Formula: see text]nm CNTFET technology from the Stanford University.

scholarly journals Investigation of Multiple-valued Logic Technologies for Beyond-binary Era

2021 ◽  
Vol 54 (1) ◽  
pp. 1-30
Author(s):  
Zarin Tasnim Sandhie ◽  
Jill Arvindbhai Patel ◽  
Farid Uddin Ahmed ◽  
Masud H. Chowdhury
Keyword(s):  
Processing Speed ◽  
Number System ◽  
Ternary Logic ◽  
Binary Logic ◽  
Multiple Valued Logic ◽  
Real World Applications ◽  
Effective Synthesis ◽  
Processing And Storage ◽  
And Storage ◽  
Logic System

Computing technologies are currently based on the binary logic/number system, which is dependent on the simple on and off switching mechanism of the prevailing transistors. With the exponential increase of data processing and storage needs, there is a strong push to move to a higher radix logic/number system that can eradicate or lessen many limitations of the binary system. Anticipated saturation of Moore’s law and the necessity to increase information density and processing speed in the future micro and nanoelectronic circuits and systems provide a strong background and motivation for the beyond-binary logic system. In this review article, different technologies for Multiple-valued-Logic (MVL) devices and the associated prospects and constraints are discussed. The feasibility of the MVL system in real-world applications rests on resolving two major challenges: (i) development of an efficient mathematical approach to implement the MVL logic using available technologies, and (ii) availability of effective synthesis techniques. This review of different technologies for the MVL system is intended to perform a comprehensive investigation of various MVL technologies and a comparative analysis of the feasible approaches to implement MVL devices, especially ternary logic.

scholarly journals Speedup of logic programs by binarization and partial deduction

2004 ◽  
Vol 4 (3) ◽  
pp. 355-369
Author(s):  
JAN HRŮZA ◽  
PETER šTĚPÁNEK
Keyword(s):  
Program Transformation ◽  
Logic Program ◽  
Logic Programs ◽  
Binary Logic ◽  
Partial Deduction ◽  
Binary Program ◽  
Binary Programs

Binary logic programs can be obtained from ordinary logic programs by a binarizing transformation. In most cases, binary programs obtained this way are less efficient than the original programs. (Demoen, 1992) showed an interesting example of a logic program whose computational behaviour was improved when it was transformed to a binary program and then specialized by partial deduction. The class of B-stratifiable logic programs is defined. It is shown that for every B-stratifiable logic program, binarization and subsequent partial deduction produce a binary program which does not contain variables for continuations introduced by binarization. Such programs usually have a better computational behaviour than the original ones. Both binarization and partial deduction can be easily automated. A comparison with other related approaches to program transformation is given.

scholarly journals A cor do tempo no andamento das letras: Notas entre o preto e o branco na passagem da oralidade ao letramento

2017 ◽  
Vol 25 ◽  
pp. 99
Author(s):  
Cláudia Bechara Fröhlich ◽  
Simone Moschen
Keyword(s):  
Elementary Schools ◽  
Daily Life ◽  
Rio Grande ◽  
The State ◽  
Literacy Teachers ◽  
Rio Grande Do Sul ◽  
Ternary Logic ◽  
Binary Logic ◽  
Ongoing Process ◽  
Logical Time

Based on the experience with literacy teachers from Rio Grande do Sul elementary schools, we aim to make visible an apparently invisible thread between time and passage from orality to literacy. As a way of photographing the school daily life and emphasizing different shades of a non-dictionary registered color, the color of time, we combine this reflection with the time of understanding – Lacan’s concept of logical time – lenses to see, which allowed the proposal of the fall of the school’s binary logic of alphabetization or non-alphabetization (as they are studied in Brazil). The welcoming of a ternary logic, a time of passage in which one is simultaneously in the state of alphabetization and non-alphabetization, helps to evidence an ongoing process towards the literate position, an approach that considers the uniqueness and the desire in the process of literacy.

scholarly journals Design and Implementation of Ternary Logic Circuits for VLSI Applications

2020 ◽  
Vol 9 (4) ◽  
pp. 3117-3121
Keyword(s):  
Power Dissipation ◽  
Digital Circuits ◽  
Propagation Delay ◽  
Logic Circuits ◽  
Combinational Circuits ◽  
Ternary Logic ◽  
Binary Logic ◽  
Design And Implementation ◽  
Half Adder

This paper mainly concentrates on the design and implementation of ternary logic circuits. The ternary numeral system has its base as 3. Ternary logic will use three symbols, which are, 0,1 and 2. The ternary logic has significant merits over binary logic in designing digital circuits. In this paper, it is proposed to implement a half adder circuit using ternary 3 to 1 multiplexer. The main objective of the work is, to design and implement ternary logic circuits and to analyse the function of the ternary combinational circuits using mentor graphics tool in 90nm technology. This paper also compares the ternary half adder design using k-map method with the proposed ternary half adder using multiplexer in terms of power dissipation, propagation delay and transistor count

scholarly journals Coding-Decoding Ternary Logic

2014 ◽  
Vol 10 (1) ◽  
pp. 24-32
Author(s):  
Rawnaq Habeeb
Keyword(s):  
General Purpose ◽  
Design Technique ◽  
Ternary Logic ◽  
Binary Logic ◽  
Digital Devices ◽  
Front End ◽  
Output Side ◽  
Simulation Results

In this paper ternary logic is encoded into binary and certain processes were conducted on binary logic after which the binary is decoded to ternary. General purpose digital devices were used and the circuit is designed back to front starting from ternary logic provided by transistor pairs at output side back to front end. This provided easier design technique in this particular paper. Practical and simulation results are recorded.

scholarly journals The BinProlog experience: Architecture and implementation choices for continuation passing Prolog and first-class logic engines

2011 ◽  
Vol 12 (1-2) ◽  
pp. 97-126 ◽  
Author(s):  
PAUL TARAU
Keyword(s):  
Data Representation ◽  
Runtime System ◽  
Logic Programs ◽  
Short History ◽  
Abstract Machine ◽  
Binary Logic ◽  
History Of ◽  
Source Level ◽  
Warren Abstract Machine

AbstractWe describe theBinPrologsystem's compilation technology, runtime system and its extensions supporting first-class Logic Engines while providing a short history of its development, details of some of its newer re-implementations as well as an overview of the most important architectural choices involved in their design. With focus on its differences with conventional Warren Abstract Machine (WAM) implementations, we explain key details ofBinProlog's compilation technique, which replaces the WAM with a simplifiedcontinuation passingruntime system (the “BinWAM”), based on a mapping of full Prolog tobinary logic programs. This is followed by a description of aterm compressiontechnique using a “tag-on-data” representation. Later derivatives, the Java-basedJinni Prologcompiler and the recently developedLean Prologsystem refine theBinPrologarchitecture withfirst-class Logic Engines, made generic through the use of anInteractorinterface. An overview of their applications with focus on the ability to express at source level a wide variety of Prolog built-ins and extensions covers these newer developments.

scholarly journals Design of a High Performance 4-Bit Ternary Multiplier using CNTFET

2019 ◽  
Vol 9 (2) ◽  
pp. 3106-3111
Keyword(s):  
High Performance ◽  
Field Effect Transistors ◽  
Logic Circuits ◽  
Ternary Logic ◽  
Chip Area ◽  
Binary Logic ◽  
Digital World ◽  
Multiple Valued Logic ◽  
Carbon Nano Tubes ◽  
Carbon Nano Tube

In digital world, digital circuits are influenced by binary logic. Ternary logic which follows the multiple valued logic concept for designing the logic circuits which is an great alternate to the normal binary logic due to its less power consumption and chip area is reduces. Carbon Nano-tube Field-Effect Transistors (CNTFET) is selected to implement the ternary logic circuits due to its mechanical , electrical and thermal properties. The unique feature of CNTFETs has the potential of getting required threshold voltage by varying the diameter of carbon nano-tubes that makes them as a best appropriate type for implementing the ternary logic. In this paper a 4-Bit Ternary Multiplier is designed using 1-Bit ternary multiplier by CNTFET 32nm technology node and simulated in Hspice tool. The proposed 1-Bit multiplier has 10% less delay and 18% less power than the 1-Bit multiplier proposed by Srivasu et al.

scholarly journals Application three-valued logic in symmetric block encryption algorithms

2021 ◽  
Vol 2131 (2) ◽  
pp. 022082
Author(s):  
T R Abdullaev ◽  
G U Juraev
Keyword(s):  
Information Technologies ◽  
Number System ◽  
Symmetric Encryption ◽  
Informational Entropy ◽  
Ternary Logic ◽  
Random Data ◽  
Binary Logic ◽  
Encryption Algorithms ◽  
Further Development ◽  
Symmetric Block

Abstract The issues of limiting the use of binary logic for the further development of science engineering are discussed. The effectiveness of the use of the ternary number system at this stage in the development of information technologies is substantiated and shown. A method is proposed for increasing the informational entropy of plaintext by adding random data using ternary logic in the process of symmetric encryption. To reliably hide the added random data, the first transforming function is proposed to choose gamming with a key.

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