scholarly journals Design and Implementation of Ternary Logic Circuits for VLSI Applications

2020 ◽  
Vol 9 (4) ◽  
pp. 3117-3121
Keyword(s):  
Power Dissipation ◽  
Digital Circuits ◽  
Propagation Delay ◽  
Logic Circuits ◽  
Combinational Circuits ◽  
Ternary Logic ◽  
Binary Logic ◽  
Design And Implementation ◽  
Half Adder

This paper mainly concentrates on the design and implementation of ternary logic circuits. The ternary numeral system has its base as 3. Ternary logic will use three symbols, which are, 0,1 and 2. The ternary logic has significant merits over binary logic in designing digital circuits. In this paper, it is proposed to implement a half adder circuit using ternary 3 to 1 multiplexer. The main objective of the work is, to design and implement ternary logic circuits and to analyse the function of the ternary combinational circuits using mentor graphics tool in 90nm technology. This paper also compares the ternary half adder design using k-map method with the proposed ternary half adder using multiplexer in terms of power dissipation, propagation delay and transistor count

Study and Performance Analysis of MOS Technology and Nanocomputing QCA

2017 ◽  
Vol 9 (02) ◽  
pp. 93-96
Author(s):  
Vinay Kumar Verma ◽  
Neeraj Kumar Misra
Keyword(s):  
Information Flow ◽  
Power Dissipation ◽  
Digital Circuits ◽  
Combinational Circuits ◽  
Analysis And Design ◽  
Critical Issues ◽  
Simulation Purpose ◽  
And Performance ◽  
Synthesis Approach ◽  
Computing Speed

One of the critical issues in VLSI circuit is High Power dissipation. Quantumdot Cellular Automata (QCA) which is widely utilized in nanocomputing era. QCA has Landauer clocked based synthesis approach and it has clocked based information flow. This manuscript analysis and design a combinational digital circuits in an emerging QCA framework. The design is evaluated and formulated in terms of area, latency and power dissipation. QCA Designer tool has been taken for the design of quantum cell-based combinational circuits and simulation purpose. Moreover, it is believed based on experimental analysis that the QCA based combination circuits will make a contribution to high computing speed and low power paradigm.

DYNAMIC GaAs LOGIC CIRCUITS

1991 ◽  
Vol 02 (03) ◽  
pp. 163-183
Author(s):  
DAVID H.K. HOE ◽  
C. ANDRE T. SALAMA
Keyword(s):  
Power Dissipation ◽  
Clock Cycle ◽  
Dynamic Logic ◽  
Logic Circuits ◽  
System Throughput ◽  
Leakage Currents ◽  
Design And Implementation ◽  
Main Challenge ◽  
Dynamic Circuits ◽  
Functional Blocks

Because of their ratioless nature, dynamic logic has several advantages over conventional static techniques used in GaAs . The ability to implement complex gates with dynamic logic leads to circuits with increased speed and reduced power dissipation. Several dynamic configurations using GaAs MESFETs are reviewed. The main challenge is to overcome leakage currents associated with the Schottky gate junctions in order to allow reliable dynamic operation. The pipelining of GaAs dynamic circuits, which allows full use of the clock cycle and improves system throughput, is also discussed. The feasibility of using these dynamic designs in GaAs is illustrated through the design and implementation of complex functional blocks.

scholarly journals Urdhva Tiryak Sutra Based Ancient Multiplication in Reversible Logic Circuits

2020 ◽  
Vol 9 (5) ◽  
pp. 685-697
Keyword(s):  
Error Detection ◽  
Power Dissipation ◽  
Digital Circuits ◽  
Vlsi Design ◽  
Logic Circuits ◽  
Arithmetic Logic Unit ◽  
Computation Algorithm ◽  
Speed And Accuracy ◽  
Quantum Parameters ◽  
Logic Unit

The proposed work analyses the employment of an ancient mathematical approach for building an arithmetic logic unit. Dissipation of power is one of the major driving issues in VLSI design. With the assistance of reversible gates, the power dissipation and loss of information can be minimized. The speed and accuracy of the Arithmetic Logic Unit depends on the propagator. Employing the traditional mathematics sutras technique within the computation algorithm reduces the complexity, duration and power. Due to the effect of environmental factors on the digital circuits, parity conserving technique is incorporated for providing error detection ability. The proposed work deal with the design and analysis of 32 bit reversible multiplier using ancient sutras with and without parity conserving technique .The planned work is implemented on Xilinx ISE Spartan 6E series of FPGA and simulation results are obtained. By using Cadence EDA tool, power, area and delay are calculated. The quantum parameters are calculated manually for 32-bit reversible multiplier using ancient technique with and without parity conserving technique using Urdhva Tiryakbhyam sutra.

scholarly journals Performance Comparison of Digital Circuits Using Subthreshold Leakage Power Reduction Techniques

2017 ◽  
Vol 14 (1) ◽  
pp. 74 ◽  
Author(s):  
B. Kalagadda ◽  
N. Muthyala ◽  
K.K. Korlapati
Keyword(s):  
Power Dissipation ◽  
Digital Circuits ◽  
Digital Circuit ◽  
Performance Comparison ◽  
Power Reduction ◽  
Leakage Power ◽  
Nand Gate ◽  
Reduction Techniques ◽  
Half Adder ◽  
Subthreshold Leakage

Complementary metal-oxide semiconductors (CMOS), stack, sleep and sleepy keeper techniques are used to control sub-threshold leakage. These effective low-power digital circuit design approaches reduce the overall power dissipation. In this paper, the characteristics of inverter, twoinput negative-AND (NAND) gate, and half adder digital circuits were analyzed and compared in 45nm, 120nm, 180nm technology nodes by applying several leakage power reduction methodologies to conventional CMOS designs. The sleepy keeper technique when compared to other techniques dissipates less static power. The advantage of the sleepy keeper technique is mainly its ability to preserve the logic state of a digital circuit while reducing subthreshold leakage power dissipation. 

scholarly journals Design of a High Performance 4-Bit Ternary Multiplier using CNTFET

2019 ◽  
Vol 9 (2) ◽  
pp. 3106-3111
Keyword(s):  
High Performance ◽  
Field Effect Transistors ◽  
Logic Circuits ◽  
Ternary Logic ◽  
Chip Area ◽  
Binary Logic ◽  
Digital World ◽  
Multiple Valued Logic ◽  
Carbon Nano Tubes ◽  
Carbon Nano Tube

In digital world, digital circuits are influenced by binary logic. Ternary logic which follows the multiple valued logic concept for designing the logic circuits which is an great alternate to the normal binary logic due to its less power consumption and chip area is reduces. Carbon Nano-tube Field-Effect Transistors (CNTFET) is selected to implement the ternary logic circuits due to its mechanical , electrical and thermal properties. The unique feature of CNTFETs has the potential of getting required threshold voltage by varying the diameter of carbon nano-tubes that makes them as a best appropriate type for implementing the ternary logic. In this paper a 4-Bit Ternary Multiplier is designed using 1-Bit ternary multiplier by CNTFET 32nm technology node and simulated in Hspice tool. The proposed 1-Bit multiplier has 10% less delay and 18% less power than the 1-Bit multiplier proposed by Srivasu et al.

scholarly journals A Comparative Review on ALU using CMOS and GDI techniques for Power Dissipation and Propagation Delay

IJOSTHE ◽  
2020 ◽  
Vol 7 (1) ◽  
pp. 4
Author(s):  
Rimjhim Saxena ◽  
Kiran Sharma
Keyword(s):  
Power Consumption ◽  
Power Dissipation ◽  
High Speed ◽  
Digital Signal ◽  
Propagation Delay ◽  
Logic Circuits ◽  
Compact Size ◽  
Comparative Review ◽  
Basic Functions ◽  
The One

Arithmetic and Logic Circuits are to be designed with less power, compact size, less propagation delay in this fast growing era of technology. Arithmetic operations are indispensable and the basic functions for any high speed low power applications like digital signal processing, microprocessors, image processing, etc. Consumption of power is the major issue in designing these circuits. Also the number of transistors required is also the one of the issues in designing the circuits. To minimize the transistors required in designing the circuits and to reduce the power consumption of the circuits, the authors have referred some techniques to overcome these problems in this paper. By reviewing all these techniques, the authors try to implement the GDI technique to reduce the power consumption and transistors count or the area required to design the circuits.

Novel Approach to Design DPL-based Ternary Logic Circuits

2018 ◽  
Author(s):  
Narendra Deo Singh ◽  
Rakesh Kumar Singh ◽  
Rahul Raj ◽  
Shivam Jyoti ◽  
Aloke Saha
Keyword(s):  
Logic Circuits ◽  
Ternary Logic ◽  
Novel Approach
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