A Universal Method for Designing Multi-Digit Ternary to Binary Converter Using CNTFET

2020 ◽  
Vol 29 (12) ◽  
pp. 2050196 ◽  
Author(s):  
Maryam Shahangian ◽  
Seied Ali Hosseini ◽  
Reza Faghih Mirzaee
Keyword(s):  
Threshold Voltage ◽  
High Efficiency ◽  
Field Effect Transistors ◽  
Block Diagram ◽  
Universal Method ◽  
Ternary Logic ◽  
Chip Area ◽  
Binary Logic ◽  
Multiple Valued Logic ◽  
Essential Components

Ternary logic can reduce the number of interconnections, chip area and power dissipation. In addition, one of the important features of carbon nanotube field effect transistors (CNTFETs) is the capability of adjusting threshold voltage. As a result, the design complexity of ternary circuits can be decreased. The structure of a mixed radix system which is based on multi-valued and binary logic is more appropriate compared to only multiple-valued logic (MVL). Therefore, ternary-to-binary and binary-to-ternary converters are the essential components for the ternary signaling on the bus and the binary logic processing circuits. It is also important for the creation of compatibility between the binary and ternary logic. This study is about a multi-digit binary-to-ternary converter by using CNTFET. At first, the algorithm used for the multi-digit conversion from ternary to binary logic is addressed in this paper. Then, the paper proposes a block diagram suitable for designing the multi-digit ternary-to-binary converter. Some new gates including One-Active Gate and Two-Active Gate, as well as two types of binary half-and full-adders, are designed for the purpose of implementing the proposed block diagram. This is done by adjusting the proper threshold voltage for CNTFETs. The proposed algorithm can also be applied to any desired number of bits. The proper operation and high efficiency of the proposed converter are confirmed by HSPICE simulation results and 32[Formula: see text]nm CNTFET technology from the Stanford University.

scholarly journals Design of a High Performance 4-Bit Ternary Multiplier using CNTFET

2019 ◽  
Vol 9 (2) ◽  
pp. 3106-3111
Keyword(s):  
High Performance ◽  
Field Effect Transistors ◽  
Logic Circuits ◽  
Ternary Logic ◽  
Chip Area ◽  
Binary Logic ◽  
Digital World ◽  
Multiple Valued Logic ◽  
Carbon Nano Tubes ◽  
Carbon Nano Tube

In digital world, digital circuits are influenced by binary logic. Ternary logic which follows the multiple valued logic concept for designing the logic circuits which is an great alternate to the normal binary logic due to its less power consumption and chip area is reduces. Carbon Nano-tube Field-Effect Transistors (CNTFET) is selected to implement the ternary logic circuits due to its mechanical , electrical and thermal properties. The unique feature of CNTFETs has the potential of getting required threshold voltage by varying the diameter of carbon nano-tubes that makes them as a best appropriate type for implementing the ternary logic. In this paper a 4-Bit Ternary Multiplier is designed using 1-Bit ternary multiplier by CNTFET 32nm technology node and simulated in Hspice tool. The proposed 1-Bit multiplier has 10% less delay and 18% less power than the 1-Bit multiplier proposed by Srivasu et al.

scholarly journals Investigation of Multiple-valued Logic Technologies for Beyond-binary Era

2021 ◽  
Vol 54 (1) ◽  
pp. 1-30
Author(s):  
Zarin Tasnim Sandhie ◽  
Jill Arvindbhai Patel ◽  
Farid Uddin Ahmed ◽  
Masud H. Chowdhury
Keyword(s):  
Processing Speed ◽  
Number System ◽  
Ternary Logic ◽  
Binary Logic ◽  
Multiple Valued Logic ◽  
Real World Applications ◽  
Effective Synthesis ◽  
Processing And Storage ◽  
And Storage ◽  
Logic System

Computing technologies are currently based on the binary logic/number system, which is dependent on the simple on and off switching mechanism of the prevailing transistors. With the exponential increase of data processing and storage needs, there is a strong push to move to a higher radix logic/number system that can eradicate or lessen many limitations of the binary system. Anticipated saturation of Moore’s law and the necessity to increase information density and processing speed in the future micro and nanoelectronic circuits and systems provide a strong background and motivation for the beyond-binary logic system. In this review article, different technologies for Multiple-valued-Logic (MVL) devices and the associated prospects and constraints are discussed. The feasibility of the MVL system in real-world applications rests on resolving two major challenges: (i) development of an efficient mathematical approach to implement the MVL logic using available technologies, and (ii) availability of effective synthesis techniques. This review of different technologies for the MVL system is intended to perform a comprehensive investigation of various MVL technologies and a comparative analysis of the feasible approaches to implement MVL devices, especially ternary logic.

Double‐Gate MoS 2 Field‐Effect Transistors with Full‐Range Tunable Threshold Voltage for Multifunctional Logic Circuits

2021 ◽  
pp. 2101036
Author(s):  
Jiali Yi ◽  
Xingxia Sun ◽  
Chenguang Zhu ◽  
Shengman Li ◽  
Yong Liu ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Full Range ◽  
Logic Circuits ◽  
Double Gate

Threshold-Voltage-Shift Mechanism in Pentacene Field Effect Transistors Caused by Photoirradiation

2008 ◽  
Vol 47 (4) ◽  
pp. 3189-3192 ◽  
Author(s):  
Chang Bum Park ◽  
Takamichi Yokoyama ◽  
Tomonori Nishimura ◽  
Koji Kita ◽  
Akira Toriumi
Keyword(s):  
Threshold Voltage ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Threshold Voltage Shift ◽  
Voltage Shift

scholarly journals The gamma-ray irradiation sensitivity and dosimetric information instability of RADFET dosimeter

2013 ◽  
Vol 28 (4) ◽  
pp. 415-421 ◽  
Author(s):  
Milic Pejovic
Keyword(s):  
Threshold Voltage ◽  
Field Effect ◽  
Room Temperature ◽  
Gamma Ray ◽  
Field Effect Transistors ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Threshold Voltage Shift ◽  
Voltage Shift ◽  
Gamma Ray Irradiation

The gamma-ray irradiation sensitivity to radiation dose range from 0.5 Gy to 5 Gy and post-irradiation annealing at room and elevated temperatures have been studied for p-channel metal-oxide-semiconductor field effect transistors (also known as radiation sensitive field effect transistors or pMOS dosimeters) with gate oxide thicknesses of 400 nm and 1 mm. The gate biases during the irradiation were 0 and 5 V and 5 V during the annealing. The radiation and the post-irradiation sensitivity were followed by measuring the threshold voltage shift, which was determined by using transfer characteristics in saturation and reader circuit characteristics. The dependence of threshold voltage shift DVT on absorbed radiation dose D and annealing time was assessed. The results show that there is a linear dependence between DVT and D during irradiation, so that the sensitivity can be defined as DVT/D for the investigated dose interval. The annealing of irradiated metal-oxide-semiconductor field effect transistors at different temperatures ranging from room temperature up to 150?C was performed to monitor the dosimetric information loss. The results indicated that the dosimeters information is saved up to 600 hours at room temperature, whereas the annealing at 150?C leads to the complete loss of dosimetric information in the same period of time. The mechanisms responsible for the threshold voltage shift during the irradiation and the later annealing have been discussed also.

Controlling the threshold voltage of β-Ga2O3 field-effect transistors via remote fluorine plasma treatment

2019 ◽  
Vol 7 (29) ◽  
pp. 8855-8860 ◽  
Author(s):  
Janghyuk Kim ◽  
Marko J. Tadjer ◽  
Michael A. Mastro ◽  
Jihyun Kim
Keyword(s):  
Plasma Treatment ◽  
Threshold Voltage ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Double Gate ◽  
Metal Insulator ◽  
Metal Insulator Semiconductor ◽  
Enhancement Mode ◽  
Mode Operation

The threshold voltage of β-Ga2O3 metal–insulator–semiconductor field-effect transistors is controlled via remote fluorine plasma treatment, enabling an enhancement-mode operation under double gate condition.

scholarly journals Implementation of Unbalanced Ternary Logic Gates with the Combination of Spintronic Memristor and CMOS

Electronics ◽  
2020 ◽  
Vol 9 (4) ◽  
pp. 542 ◽  
Author(s):  
Haifeng Zhang ◽  
Zhaowei Zhang ◽  
Mingyu Gao ◽  
Li Luo ◽  
Shukai Duan ◽  
...  
Keyword(s):  
High Efficiency ◽  
Load Capacity ◽  
Complementary Metal Oxide Semiconductor ◽  
Logic Gates ◽  
Logic Circuit ◽  
Oxide Semiconductor ◽  
Ternary Logic ◽  
Logic Operations ◽  
Almost All ◽  
Logic Functions

A memristor is a nanoscale electronic element that displays a threshold property, non-volatility, and variable conductivity. Its composite circuits are promising for the implementation of intelligence computation, especially for logic operations. In this paper, a flexible logic circuit composed of a spintronic memristor and complementary metal-oxide-semiconductor (CMOS) switches is proposed for the implementation of the basic unbalanced ternary logic gates, including the NAND, NOR, AND, and OR gates. Meanwhile, due to the participation of the memristor and CMOS, the proposed circuit has advantages in terms of non-volatility and load capacity. Furthermore, the input and output of the proposed logic are both constant voltages without signal degradation. All these three merits make the proposed circuit capable of realizing the cascaded logic functions. In order to demonstrate the validity and effectiveness of the entire work, series circuit simulations were carried out. The experimental results indicated that the proposed logic circuit has the potential to realize almost all basic ternary logic gates, and even some more complicated cascaded logic functions with a compact circuit construction, high efficiency, and good robustness.

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