Correctness of Synthesis for Tree based Decomposed Algorithm in Semiconductor Memory Designs with Larger Decoders

The I/О synchronization scheme plays an important role in achieving maximum speed and reliability of data transmission during memory operation. This paper presents the interface architecture of the DDR SDRAM test diagnostic device. It was demonstrated that the proposed interface components provide the formation of a bidirectional synchro signal for gating written and read data when performing test diagnostics of chips and DDR SDRAM memory devices. Compared to traditional methods, the proposed interface components were made on integrated electronic elements, which reduced the size and power consumption. It has been established that the use of a multiphase synchronization system to implement the interface eliminated the use of delay lines, the disadvantages of which are large dimensions and the complexity of changing the delay time. The interface components under consideration are intended for use in test diagnostics devices that have a multiprocessor structure, which increases the speed of forming test actions and reference reactions. The performed functional modeling and debugging of strobe signal generators confirmed the feasibility of the designs. The proposed interface of the test diagnostics device allows performing test diagnostics of modern high-speed chips and semiconductor memory modules at the operating frequency, which increases the reliability of the results obtained. Interface components can be used by manufacturers of test diagnostics tools for modern high-speed storage devices.

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Design and Analysis of SRAM Cell using Negative Bit-Line Write Assist Technique and Separate Read Port for High-Speed Applications

Journal of Circuits System and Computers ◽

10.1142/s0218126621502704 ◽

2021 ◽

pp. 2150270

Author(s):

Jitendra Kumar Mishra ◽

Lakshmi Likhitha Mankali ◽

Kavindra Kandpal ◽

Prasanna Kumar Misra ◽

Manish Goswami

Keyword(s):

Power Dissipation ◽

High Speed ◽

Random Access ◽

Random Access Memory ◽

Access Memory ◽

Static Noise Margin ◽

Semiconductor Memory ◽

Noise Margin ◽

Sram Cell ◽

Static Noise

The present day electronic gadgets have semiconductor memory devices to store data. The static random access memory (SRAM) is a volatile memory, often preferred over dynamic random access memory (DRAM) due to higher speed and lower power dissipation. However, at scaling down of technology node, the leakage current in SRAM often increases and degrades its performance. To address this, the voltage scaling is preferred which subsequently affects the stability and delay of SRAM. This paper therefore presents a negative bit-line (NBL) write assist circuit which is used for enhancing the write ability while a separate (isolated) read buffer circuit is used for improving the read stability. In addition to this, the proposed design uses a tail (stack) transistor to decrease the overall static power dissipation and also to maintain the hold stability. The comparison of the proposed design has been done with state-of-the-art work in terms of write static noise margin (WSNM), write delay, read static noise margin (RSNM) and other parameters. It has been observed that there is an improvement of 48%, 11%, 19% and 32.4% in WSNM while reduction of 33%, 39%, 48% and 22% in write delay as compared to the conventional 6T SRAM cell, NBL, [Formula: see text] collapse and 9T UV SRAM, respectively.

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