Wire bonding process impact on low-k dielectric material in damascene copper integrated circuits

2003 ◽  
Author(s):  
V. Kripesh ◽  
M. Sivakumar ◽  
Loon Aik Lim ◽  
R. Kumar ◽  
M.K. Iyer
Keyword(s):  
Integrated Circuits ◽  
Dielectric Material ◽  
Wire Bonding ◽  
Bonding Process ◽  
Low K

Reliability of Wire Bonding on Low-k Dielectric Material in Damascene Copper Integrated Circuits PBGA Assembly

2002 ◽  
Vol 42 (9-11) ◽  
pp. 1535-1540 ◽  
Author(s):  
Mohandass Sivakumar ◽  
Vaidyanathan Kripesh ◽  
Chong Ser Choong ◽  
Chai Tai Chong ◽  
Loon Aik Lim
Keyword(s):  
Integrated Circuits ◽  
Dielectric Material ◽  
Wire Bonding ◽  
Low K

Study of Porous Silica Based Films as Low-k Dielectric Material and their Interface with Copper Metallization

2002 ◽  
Vol 716 ◽  
Author(s):  
Ilanit Fisher ◽  
Wayne D. Kaplan ◽  
Moshe Eizenberg ◽  
Michael Nault ◽  
Timothy Weidman
Keyword(s):  
Integrated Circuits ◽  
Dielectric Material ◽  
Hydrogen Plasma ◽  
Porous Silica ◽  
Film Deposition ◽  
Copper Metallization ◽  
High Porosity ◽  
Tem Analysis ◽  
Chip Technology ◽  
Low K

AbstractThe success of future gigascale integrated circuits (IC) chip technology depends critically upon the reduction of the interconnects RC delay time. This calls for the development of new low dielectric constant (low-k) insulators, and for work on their integration with lower resistivity copper metallization.A porous silica based film prepared by surfactant templated self-assembly spin-on deposition (SOD) is an attractive candidate as a low-k material. In this research we have studied the structure, chemical composition and bonding of the film and its interface with copper metallization. The decomposition and vaporization of the surfactant in the last step of film deposition resulted in a film with an amorphous structure, as determined by XRD and TEM analysis. Its high porosity (35-58%) was confirmed by XRR and RBS measurements. XPS analysis of the Si2p transition indicated three types of bonding: Si-O, O-Si-C and Si-C. The bonding characteristics were also investigated by FTIR analysis. The effect of a hydrogen plasma post-treatment process on the film topography and bonding was determined by AFM and XPS, respectively. It was found that direct H2 plasma exposure significantly affected the surface roughness of the film and type of chemical bonding. The structure and properties of various PECVD deposited capping layers were also studied, as was the interface between the porous dielectric and Ta, TaxN and Cu (PVD deposited films) after annealing at 200-700°C in vacuum environment for 30 min. At temperatures up to 500°C, no significant diffusion of Cu or Ta into the porous film was detected, as determined by RBS. No copper penetration was detected up to 700°C, according to AES and SIMS analysis. However, at 700°C copper dewetting occurred when it was deposited directly on the porous silica based film.

Wire-bonding process development for low-k materials

2005 ◽  
Vol 81 (1) ◽  
pp. 75-82 ◽  
Author(s):  
Jonathan Tan ◽  
Zhao Wei Zhong ◽  
Hong Meng Ho
Keyword(s):  
Process Development ◽  
Wire Bonding ◽  
Bonding Process ◽  
Low K

Surfactants in Controlling Removal Rates and Selectivity in Barrier Slurry for Cu CMP

2007 ◽  
Vol 991 ◽  
Author(s):  
Jinru Bian
Keyword(s):  
Integrated Circuits ◽  
Dielectric Material ◽  
Removal Rate ◽  
Leading Edge ◽  
Dielectric Surface ◽  
Wafer Surface ◽  
Capping Layer ◽  
Charge Interaction ◽  
High Removal Rate ◽  
Low K

ABSTRACTLeading edge integrated circuits (ICs) are complicated structures designed to have up to 3 capping layers above a low k dielectric material. The upper capping layer may use TEOS and/or silicon nitride (SiN), while the lower one may use silicon carbon nitride (SiCN), silicon carbide (SiC), or carbon doped oxide (CDO) immediately above the low k dielectric. Therefore, a barrier slurry for copper CMP, in addition to exhibiting a high removal rate of the barrier, must be able to remove the upper capping layer and stop at the underlying dielectric surface.We have developed a slurry family that can effectively remove TaN, TEOS, SiN, CDO, and/or SiCN, or any combination of these films, or can stop at any one or two film surfaces of TEOS, SiN, CDO, SiCN, and SiC, depending on the specific slurry design. Removal rate control is achieved by one or two additives. One of the additives is an anionic surfactant. When selecting a surfactant, the surfactant hydrophobicity and charge interaction between the surfactant and the wafer surface are two important factors to be considered. This report discusses these two factors in selecting a proper surfactant for a specific slurry application.

Numerical Study of Gold Wire Bonding Process on Cu/Low-k Structures

2007 ◽  
Vol 30 (3) ◽  
pp. 448-456 ◽  
Author(s):  
Akella G. K. Viswanath ◽  
Xiaowu Zhang ◽  
V. P. Ganesh ◽  
Lu Chun
Keyword(s):  
Numerical Study ◽  
Gold Wire ◽  
Wire Bonding ◽  
Bonding Process ◽  
Low K

Development of a New Wire Bonding Technology on Integrated Circuit Devices

2009 ◽  
Author(s):  
Yingwei Jiang ◽  
Ronglu Sun ◽  
Sonder Wang ◽  
C. L. Zhang ◽  
Youmin Yu ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Copper Wire ◽  
Electrical Characterization ◽  
Wire Bonding ◽  
Bonding Process ◽  
Process Window ◽  
Temperature Cycle ◽  
Tool Selection ◽  
Bonding Technology ◽  
Gold Bump

In IC packaging, copper wire is generally regarded as a competent successor to gold wire due to many advantages in mechanical characteristics and cost efficiency. However, its known disadvantages restrict it to low-end integrated circuits as well. This paper discusses the development of a new wire bonding technology — copper ball on gold bump (COG) bonding in current wire bonders with both 1 mil copper and gold wires. It covers material and tool selection, wire bonding process window development, electrical characterization and reliability studies. The material and tool selection includes copper wire, experimental chip, capillary and wire bonder. Process window development focuses on two crucial stages, copper free air ball (FAB) formation and bonding process window development for both gold bump and copper ball bonded on Au bump. DOE approach is introduced into the relative process developments. The experimental studies reveal that flow rate of shielding gas is a key factor to obtain the qualified FAB formation and process window optimization for gold bump and copper ball on gold bump is more crucial to develop a successful COG bonding. Wire pull test, ball shear test and crater test are involved in the output measurement based on the criteria of JEDEC during the process window development. Package integrity and reliability performance with the COG bonding are fully assessed by performing electrical characterization and package internal delamination detection on the evaluated samples which have respectively undergone three reliability tests, High Temperature Baking, Temperature Cycle and Autoclave. The study result finally indicates that the COG bonding is a practicable approach to achieving copper wire application to high-end integrated circuits.

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