Surfactants in Controlling Removal Rates and Selectivity in Barrier Slurry for Cu CMP

2007 ◽  
Vol 991 ◽  
Author(s):  
Jinru Bian
Keyword(s):  
Integrated Circuits ◽  
Dielectric Material ◽  
Removal Rate ◽  
Leading Edge ◽  
Dielectric Surface ◽  
Wafer Surface ◽  
Capping Layer ◽  
Charge Interaction ◽  
High Removal Rate ◽  
Low K

ABSTRACTLeading edge integrated circuits (ICs) are complicated structures designed to have up to 3 capping layers above a low k dielectric material. The upper capping layer may use TEOS and/or silicon nitride (SiN), while the lower one may use silicon carbon nitride (SiCN), silicon carbide (SiC), or carbon doped oxide (CDO) immediately above the low k dielectric. Therefore, a barrier slurry for copper CMP, in addition to exhibiting a high removal rate of the barrier, must be able to remove the upper capping layer and stop at the underlying dielectric surface.We have developed a slurry family that can effectively remove TaN, TEOS, SiN, CDO, and/or SiCN, or any combination of these films, or can stop at any one or two film surfaces of TEOS, SiN, CDO, SiCN, and SiC, depending on the specific slurry design. Removal rate control is achieved by one or two additives. One of the additives is an anionic surfactant. When selecting a surfactant, the surfactant hydrophobicity and charge interaction between the surfactant and the wafer surface are two important factors to be considered. This report discusses these two factors in selecting a proper surfactant for a specific slurry application.

Polishing and Cleaning of Low K Dielectric Material for ild and Damascene

2001 ◽  
Vol 671 ◽  
Author(s):  
Yuchun Wang ◽  
Rajeev Bajaj ◽  
Yongsik Moon ◽  
David Mai ◽  
Kapila Wijekoon ◽  
...  
Keyword(s):  
Dielectric Material ◽  
Removal Rate ◽  
Copper Surface ◽  
Dielectric Surface ◽  
Process Technology ◽  
Future Directions ◽  
Good Surface ◽  
Cleaning Solution ◽  
Good Surface Finish ◽  
Low K

Summary:This paper describes CMP challenges in development of copper-low k process technology. As copper/oxide or copper/FSG backend schemes are being implemented successfully in early manufacturing, development focus has shifted to Cu/OSG (organo-silicate glass) integration development. Cu-OSG presents unique challenges with CMP integration, as these films tend to have much lower hardness than silicon dioxide. Significant process challenges have to be overcome prior to successfully implementing CMP process which does not mechanically damage the softer films and at the same time can achieve planarization requirements expected from CMP process. In addition, the OSG films tend to be hydrophobic leading to a need for developing improved cleaning processes/consumables. It was determined that Applied Materials ElectraPolishTM barrier slurry is extendable to OSG films. Good removal rate and removal profile can be achieved with ElectraPolishTM slurry. A proprietary cleaning solution reduced defect counts by 2 orders of magnitude as detected by SurfScan SS6200 on blanket OSG wafers. The same cleaning solution can be applied to copper/low-k patterned damascene wafers to clean both copper and dielectric surface. Polished OSG films have RMS roughness less than 2 angstroms and copper surface roughness about 5 angstroms with good surface finish. Blanket and patterned wafer results are presented to demonstrate final capability. Future directions for process enhancement are suggested.

Experimental Investigation on Chemical-Mechanical Polishing of Wafers With Low-Conductivity Dielectrics

2001 ◽  
Author(s):  
Jhy-Cherng Tsai ◽  
Charls Liu ◽  
Ming-Hsih Tsai ◽  
Bao-Tong Dai
Keyword(s):  
Chemical Mechanical Polishing ◽  
Material Removal ◽  
Sandwich Structure ◽  
Dielectric Material ◽  
Removal Rate ◽  
Mechanical Polishing ◽  
Wafer Surface ◽  
Key Technologies ◽  
Semiconductor Fabrication ◽  
Low K

Abstract Low conductivity (low-k) dielectric material is used in the sandwich structure of next-generation semiconductor devices in order to reduce the RC time delay. While global flatness of wafer surface becomes critical for deep sub-micro semiconductor fabrication process, chemical-mechanical polishing (CMP) becomes one of the key technologies for planarization of wafer surface. This paper investigated the effect of the low-k material on the CMP of the SiO2 cap layer of such a sandwiched wafer. Two types of wafers, blanket wafer and wafer with circuit pattern, are designed and conducted to investigate the effects of the thickness of the low-k layer under different polishing pressures and velocities. Material removal rate (RR) and non-uniformity (NU) are used as indices of the CMP process performance. The results show that the RR and NU of wafers with low-k layer, either blanket or with circuit pattern, become better when the pressure or velocity increases. The thickness of the low-k layer, however, has only tiny effect on the RR and NU.

Low-K Dielectric Material Chemical Mechanical Polishing Process Monitoring using Acoustic Emission

1997 ◽  
Vol 476 ◽  
Author(s):  
Jianshe Tang ◽  
Carsten Unger ◽  
Yongsik Moon ◽  
David Dornfeld
Keyword(s):  
Surface Roughness ◽  
Acoustic Emission ◽  
Material Removal Rate ◽  
Material Removal ◽  
Dielectric Material ◽  
Removal Rate ◽  
Wafer Surface ◽  
Low K ◽  
Ae Signals

AbstractLow-k dielectric material removal rate, which is significantly affected by process factors such as polishing load, wafer carrier rotation, platen rotation speed and pad age, is one of the critical issues in CMP planarization of a dielectric film when concerning productivity, throughputs and stabilization of the process, especially when trying to achieve a target polishing thickness. Scratching is another critical issue in low-k dielectric filmi CMP planarization due to the lower hardness relative to silicon dioxide. This research relates to a methodology for in-situ monitoring of the low-k dielectric material CMP planarization process, specifically for monitoring material removal rate and scratch occurrence, using acoustic emission (AE) sensing technology.Systematic investigations of CMP process variables on AE signals were carried out in this research. The sensitivity of AE to polishing load, polishing speed, wafer surface roughness (wafer pattern density) and pad roughness were verified. The results showed that, under steady state, the AE rms signal increases with increasing polishing load, polishing speed, slurry particle size, wafer surface roughness and pad roughness.Based on the research in tribology and other application fields of loose abrasive machining such as lapping and polishing, scratching was known to be caused by the presence of particles which are much larger than average slurry particles. It has been proven that scratching can be avoided or reduced by timely cleaning the slurry supply system. Therefore, to avoid scratching, one strategy is to develop an in-situ method for detecting larger particles involved in CMP process. In this paper, the high sensitivity of AE signals to the presence of larger particles during CMP was experimentally verified.

Study of Porous Silica Based Films as Low-k Dielectric Material and their Interface with Copper Metallization

2002 ◽  
Vol 716 ◽  
Author(s):  
Ilanit Fisher ◽  
Wayne D. Kaplan ◽  
Moshe Eizenberg ◽  
Michael Nault ◽  
Timothy Weidman
Keyword(s):  
Integrated Circuits ◽  
Dielectric Material ◽  
Hydrogen Plasma ◽  
Porous Silica ◽  
Film Deposition ◽  
Copper Metallization ◽  
High Porosity ◽  
Tem Analysis ◽  
Chip Technology ◽  
Low K

AbstractThe success of future gigascale integrated circuits (IC) chip technology depends critically upon the reduction of the interconnects RC delay time. This calls for the development of new low dielectric constant (low-k) insulators, and for work on their integration with lower resistivity copper metallization.A porous silica based film prepared by surfactant templated self-assembly spin-on deposition (SOD) is an attractive candidate as a low-k material. In this research we have studied the structure, chemical composition and bonding of the film and its interface with copper metallization. The decomposition and vaporization of the surfactant in the last step of film deposition resulted in a film with an amorphous structure, as determined by XRD and TEM analysis. Its high porosity (35-58%) was confirmed by XRR and RBS measurements. XPS analysis of the Si2p transition indicated three types of bonding: Si-O, O-Si-C and Si-C. The bonding characteristics were also investigated by FTIR analysis. The effect of a hydrogen plasma post-treatment process on the film topography and bonding was determined by AFM and XPS, respectively. It was found that direct H2 plasma exposure significantly affected the surface roughness of the film and type of chemical bonding. The structure and properties of various PECVD deposited capping layers were also studied, as was the interface between the porous dielectric and Ta, TaxN and Cu (PVD deposited films) after annealing at 200-700°C in vacuum environment for 30 min. At temperatures up to 500°C, no significant diffusion of Cu or Ta into the porous film was detected, as determined by RBS. No copper penetration was detected up to 700°C, according to AES and SIMS analysis. However, at 700°C copper dewetting occurred when it was deposited directly on the porous silica based film.

Effect of Complex Agent on Copper Dissolution in Alkaline Slurry for Chemical Mechanical Planarization

2012 ◽  
Vol 455-456 ◽  
pp. 1145-1148
Author(s):  
Yan Gang He ◽  
Jia Xi Wang ◽  
Xiao Wei Gan ◽  
Wei Juan Li ◽  
Yu Ling Liu
Keyword(s):  
Surface Roughness ◽  
Removal Rate ◽  
Chemical Mechanical Planarization ◽  
Dielectric Materials ◽  
Mechanism Analysis ◽  
Copper Dissolution ◽  
Complex Agent ◽  
High Removal Rate ◽  
Rc Delay ◽  
Low K

With the microelectronic technology node moves down to 45 nm and beyond, and to reduce the RC delay time, low-k dielectric materials have been used to replace regular dielectric materials. Therefore, the down force of chemical mechanical planarization (CMP) needs to decrease based on the characteristics of low-k materials: low mechanical strength. In this study, the effect of new complex agent on copper dissolution in alkaline slurry for CMP was investigated. Based on the reaction mechanism analysis of Cu in alkaline slurry in CMP, the performance of Cu removal rate and surface roughness condition were discussed. It has been confirmed that Cu1 slurry demonstrates a relatively high removal rate with low down force. And also, by utilizing the Cu1 slurry, good result of Cu surface roughness were obtained.

Consumables for the Chemical Mechanical Polishing (Cmp) of Dielectrics and Conductors

1994 ◽  
Vol 337 ◽  
Author(s):  
Rahul Jairath ◽  
Mukesh Desai ◽  
Matt Stell ◽  
Robert Tolles ◽  
Debra Scherber-Brewer
Keyword(s):  
Integrated Circuits ◽  
Chemical Mechanical Polishing ◽  
Large Scale ◽  
Dielectric Material ◽  
Removal Rate ◽  
Mechanical Polishing ◽  
Polished Surface ◽  
Polishing Pad ◽  
Dispersing Agent ◽  
Polishing Pressure

ABSTRACTChemical mechanical polishing (CMP) is rapidly becoming the process of choice for planarizing dielectrics in very large scale integrated circuits. In addition, it is being used at an increasing rate in the removal of metals in order to define conducting levels. In the case of dielectric CMP, planarization ability is dictated by the mechanical aspects of polishing such as pad rigidity, polishing pressure and speed of the polishing platen, while inherent removal rate of the dielectric material is generally a function of the polishing chemistry. Polishing rate of both, dielectric and metallic films can be significantly increased by changing the nature of the dispersed abrasive in the slurry and that of the dispersing agent. However, such changes have profound implications to the surface quality, planarity, and cleaning of the polished surface. In addition, the polishing pad plays an important role in manufacturability of metal CMP processes. This work reviews the chemistry of polishing slurries containing silica, ceria and alumina abrasives for dielectric and metal CMP. Also, the contribution of the polishing pad to CMP processes is explained. The need for balancing the chemical and mechanical aspects of polishing in order to achieve overall planarization and pattern definition is demonstrated.

Beveling of Silicon Carbide Wafer by Plasma Chemical Vaporization Machining

2008 ◽  
Vol 600-603 ◽  
pp. 843-846 ◽  
Author(s):  
Takehiro Kato ◽  
Yasuhisa Sano ◽  
Hideyuki Hara ◽  
Hidekazu Mimura ◽  
Kazuya Yamamura ◽  
...  
Keyword(s):  
Silicon Carbide ◽  
Atmospheric Pressure ◽  
Removal Rate ◽  
Atmospheric Pressure Plasma ◽  
High Hardness ◽  
Wafer Surface ◽  
Plasma Chemical ◽  
Pressure Plasma ◽  
Surface Polishing ◽  
High Removal Rate

Beveling is essential for preventing the chipping of the edge of a wafer during surface polishing and other processes. Plasma chemical vaporization machining (PCVM) is an atmospheric-pressure plasma etching process. It has a high removal rate equivalent to those of conventional machining methods such as grinding and lapping, which are used for high-hardness materials such as silicon carbide, due to the generation of high-density radicals in atmospheric-pressure plasma. Furthermore, PCVM does not damage the wafer surface because it is a purely chemical process; therefore, it is considered that PCVM can be used as an effective method of beveling the edge of SiC wafers. In this paper, we report the investigation of the beveling of SiC wafers by PCVM.

Removal Characteristics of Hillock Defects on Silicon Substrate by Chemical Uniformity Etching Enhanced Polishing Slurry

2012 ◽  
Vol 452-453 ◽  
pp. 219-222
Author(s):  
Ming Sun ◽  
Juan Wang ◽  
Ru Wang ◽  
Yu Ling Liu ◽  
Li Bing Yang ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Silicon Wafer ◽  
High Speed ◽  
Removal Rate ◽  
Life Time ◽  
Lower Surface ◽  
Surface Strain ◽  
Chemical Additives ◽  
Chemical Etch ◽  
High Removal Rate

The thermally generated defects will lower the life time in bulk silicon and cause increasing in the leakage current of individual diodes in integrated circuits, that will finally cause the malfunction with advanced devices and IC chips. The removal characteristics of hillock defects on the single bare silicon wafer generated by the thermal process were experimentally analysed with respect to the chemical additives enhanced uniform chemical etching and mechanical abrasion of high pure nano sphere colloidal silica interplaying with the alkali based polishing slurry. During the polishing, it was found that the silicon surface contacted with high speed of rotated polishing pad under the down force pressure is chemically dissolved by the slurry containing FA/O organic polyamine(R(NH2)n) agent with adding proper proportional FA/O I non ions surfactant, which effectively lowered the surface strain of slurry contacted to the reactive surface of the wafer and slurry enhanced uniform chemical etch leading to the hillock region and no hillock region. However, by the process of chemical mechanical polishing，the results show it can eliminate the hillock defects on the surface of silicon wafer thoroughly with high removal rate, and achieve lower surface roughness than before process of polishing.

Reliability of Wire Bonding on Low-k Dielectric Material in Damascene Copper Integrated Circuits PBGA Assembly

2002 ◽  
Vol 42 (9-11) ◽  
pp. 1535-1540 ◽  
Author(s):  
Mohandass Sivakumar ◽  
Vaidyanathan Kripesh ◽  
Chong Ser Choong ◽  
Chai Tai Chong ◽  
Loon Aik Lim
Keyword(s):  
Integrated Circuits ◽  
Dielectric Material ◽  
Wire Bonding ◽  
Low K
Sign in / Sign up

Export Citation Format

Share Document