Operational amplifier is considered as the core of the analog building blocks. High performance opamp must exhibit high gain, wide bandwidth, low power consumption and rail-to-rail output swings. In this work, we propose to design a fully-differential opamp design to satisfy certain design requirements and specifications.
The Front end read out circuits are major block in the implementation of Capacitive MEMS accelerometer. Front end read-out circuits comprises of preamplifier block containing folded cascode fully differential operational amplifier which are required for the signal conditioning of the signals received from the MEMS sensors. The op-amps are prime elements in design and implementation of mixed signal integrated circuits. The high gain and low power of the designed circuits helps in the designing of high precision IC’s for numerous application. Amongst the available topologies folded cascode topology plays vital role in the design and development of low power, high gain read out circuits. This paper illustrates the design and analysis of low power, high gain fully differential Folded Cascode Operational Amplifier for front end read out circuits. The designed op-amp exhibits a power consumption or dissipation of 92.14 μW and relatively higher open loop DC gain value with a value calculated at 81.33 dB by employing folded cascode topology. The UGB and Phase Margin for the selected design are 35 MHz and 83.60 respectively. The design operates at 5V power supply with the bias current of 12.11 μA. The circuit design and simulations have been implemented using 0.18 μm CMOS technology.
The present paper presents a fully differential 60 GHz four stages low-noise amplifier for wireless applications. The amplifier has been optimized for low-noise, high-gain, and low-power consumption, and implemented in a 90 nm low-power CMOS technology. Matching and common-mode rejection networks have been realized using shielded coplanar transmission lines. The amplifier achieves a peak small-signal gain of 21.3 dB and an average noise figure of 5.4 dB along with power consumption of 30 mW and occupying only 0.38 mm2pads included. The detailed design procedure and the achieved measurement results are presented in this work.
Fully-Differential Opamp Design
