A low-voltage low-power complex active-RC filter employing single-stage opamp

2012 ◽  
Author(s):  
Chairat Upathamkuekool ◽  
Amorn Jiraseree-amornkun ◽  
Jirayuth Mahattanakul
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Single Stage ◽  
Active Rc Filter ◽  
Power Complex

Design of Low Voltage Low Power LPF for WSN Node

2013 ◽  
Vol 760-762 ◽  
pp. 54-59
Author(s):  
Yang Lin ◽  
Zhi Qun Li ◽  
Chen Jian Wu ◽  
Meng Zhang ◽  
Zeng Qi Wang
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Frequency Tuning ◽  
Cmos Technology ◽  
Pass Band ◽  
Automatic Frequency ◽  
Temperature Deviation ◽  
Op Amp ◽  
Active Rc Filter ◽  
Operation Amplifier

A fourth-order low-pass continuous-time filter for a WSN transmitter is presented. The active RC filter was chosen for the high linearity, designed by using the leapfrog topology imitates the passive filter. The operation amplifier (op-amp) adopted by the filter is feed-forward operation amplifier, which could get the GBW as large as possible under the low power consumption. The cut-off frequency deviation due to the process corner, aging and temperature deviation is adjusted by an automatic frequency tuning circuit. The filter in a 0.18μm RF CMOS technology consumes 1mW from a 1V power supply. The measured results of the chip show that the bandwidth is about 1.5MHz. The voltage gain of filter is about-4.5dB with the buffer, the ripple in the pass-band is lower than 0.5 dB, and the channel rejection ratio is larger than 30dB at 4MHz.

DESIGN OF LOW-VOLTAGE LOW-POWER COMPLEX ACTIVE-RC FILTERS

2013 ◽  
Vol 22 (09) ◽  
pp. 1340003
Author(s):  
CHAIRAT UPATHAMKUEKOOL ◽  
AMORN JIRASEREE-AMORNKUN ◽  
JIRAYUTH MAHATTANAKUL
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Filter Design ◽  
Center Frequency ◽  
Image Rejection ◽  
Third Order ◽  
Complex Filter ◽  
Active Rc Filter ◽  
Image Rejection Ratio ◽  
Fifth Order

In this paper, novel realization of low-voltage low-power active-RC complex filters is presented. The previously proposed method to compensate for opamp non-idealities in real active-RC filter design, which is suitable for low-power low-voltage application, is extended such that it can be used in the case of complex filter design. Subsequently, fifth-order Chebyshev complex filter with 1-MHz center frequency, bandwidth and 0.5-dB bandpass ripple has been designed for Bluetooth application. Simulation results show that the designed complex filter consumes about 1 mW under 1-V single supply. Its image rejection ratio (IRR) and out-of-band third-order input intercept point (IIP3) are about 80 dB and 37.5 dBV p respectively.

Analysis of 6T SRAM Cell in Different Technologies

2017 ◽  
Vol MCSP2017 (01) ◽  
pp. 7-10 ◽  
Author(s):  
Subhashree Rath ◽  
Siba Kumar Panda
Keyword(s):  
Low Power ◽  
Data Storage ◽  
Low Voltage ◽  
Random Access ◽  
Storage Device ◽  
Cmos Process ◽  
Process Technology ◽  
Digital Devices ◽  
Noise Margin ◽  
Sram Cell

Static random access memory (SRAM) is an important component of embedded cache memory of handheld digital devices. SRAM has become major data storage device due to its large storage density and less time to access. Exponential growth of low power digital devices has raised the demand of low voltage low power SRAM. This paper presents design and implementation of 6T SRAM cell in 180 nm, 90 nm and 45 nm standard CMOS process technology. The simulation has been done in Cadence Virtuoso environment. The performance analysis of SRAM cell has been evaluated in terms of delay, power and static noise margin (SNM).

COMPOSITE TRANSISTOR CELL USING DYNAMIC BODY BIAS FOR HIGH GAIN AND LOW-VOLTAGE APPLICATIONS

2014 ◽  
Vol 23 (08) ◽  
pp. 1450108 ◽  
Author(s):  
VANDANA NIRANJAN ◽  
ASHWANI KUMAR ◽  
SHAIL BALA JAIN
Keyword(s):  
Low Power ◽  
Large Scale ◽  
Low Voltage ◽  
Supply Voltage ◽  
High Gain ◽  
Signal Frequency ◽  
Output Impedance ◽  
Self Cascode ◽  
Intrinsic Gain ◽  
Body Bias

In this work, a new composite transistor cell using dynamic body bias technique is proposed. This cell is based on self cascode topology. The key attractive feature of the proposed cell is that body effect is utilized to realize asymmetric threshold voltage self cascode structure. The proposed cell has nearly four times higher output impedance than its conventional version. Dynamic body bias technique increases the intrinsic gain of the proposed cell by 11.17 dB. Analytical formulation for output impedance and intrinsic gain parameters of the proposed cell has been derived using small signal analysis. The proposed cell can operate at low power supply voltage of 1 V and consumes merely 43.1 nW. PSpice simulation results using 180 nm CMOS technology from Taiwan Semiconductor Manufacturing Company (TSMC) are included to prove the unique results. The proposed cell could constitute an efficient analog Very Large Scale Integration (VLSI) cell library in the design of high gain analog integrated circuits and is particularly interesting for biomedical and instrumentation applications requiring low-voltage low-power operation capability where the processing signal frequency is very low.

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