Local Thermal Deformation and Residual Stress of a Thin Si Chip Mounted on a Substrate Using An Area-Arrayed Flip Chip Structure

2006 ◽  
Author(s):  
H. Miura ◽  
N. Ueta ◽  
Y. Sato
Keyword(s):  
Residual Stress ◽  
Thermal Deformation ◽  
Flip Chip

Minimization of the Local Residual Stress in 3D Flip Chip Structures by Optimizing the Mechanical Properties of Electroplated Materials and the Alignment Structure of TSVs and Fine Bumps

2011 ◽  
Author(s):  
Kohta Nakahira ◽  
Hironori Tago ◽  
Fumiaki Endo ◽  
Ken Suzuki ◽  
Hideo Miura
Keyword(s):  
Mechanical Properties ◽  
Residual Stress ◽  
Thermal Deformation ◽  
Flip Chip ◽  
Flexural Rigidity ◽  
Three Dimensional ◽  
Strain Gauges ◽  
Copper Interconnection ◽  
Induced Stress ◽  
Alignment Structure

Since the thickness of the stacked silicon chips in 3D integration has been thinned to less than 100 μm, the local thermal deformation of the chips has increased drastically because of the decrease of the flexural rigidity of the thinned chips. The clear periodic thermal deformation and thus, the thermal residual stress distribution appears in the stacked chips due to the periodic alignment of metallic bumps, and they deteriorate the reliability of products. In this paper, the dominant structural factors of the local residual stress in a silicon chip are discussed quantitatively based on the results of a three-dimensional finite element analysis and the measurement of the local residual stress in a chip using stress sensor chips. The piezoresistive strain gauges were embedded in the sensor chips. The length of each gauge was 2 μm, and an unit cell consisted of 4 gauges with different crystallographic directions. This alignment of strain gauges enables to measure the tensor component of three-dimensional stress fields separately. Test flip chip substrates were made by silicon chip on which the area-arrayed tin/copper bumps were electroplated. The width of a bump was fixed at 200 μm, and the bump pitch was varied from 400 μm to 1000 μm. The thickness of the copper layer was about 40 μm and that of tin layer was about 10 μm. This tin layer was used for the rigid joint formation by alloying with copper interconnection formed on a stress sensing chip. The measured amplitude of the residual stress increased from about 30 MPa to 250 MPa depending on the combination of materials such as bump, underfill, and interconnections. It was confirmed that both the material constant of underfill and the alignment structure of fine bumps are the dominant factors of the local deformation and stress of a silicon chip mounted on area-arrayed metallic bumps. It was also confirmed experimentally that both the hound’s-tooth alignment between a TSV (Through Silicon Via) and a bump and control of mechanical properties of electroplated copper thin films used for the TSV and bump is indispensable in order to minimize the packaging-induced stress in the three-dimensionally mounted chips. This test chip is very effective for evaluating the packaging-process induced stress in 3D stacked chips quantitatively.

Minimization of the Local Residual Stress in 3D Flip Chip Structures by Optimizing the Mechanical Properties of Electroplated Materials and the Alignment Structure of TSVs and Fine Bumps

2012 ◽  
Vol 134 (2) ◽  
Author(s):  
Kota Nakahira ◽  
Hironori Tago ◽  
Fumiaki Endo ◽  
Ken Suzuki ◽  
Hideo Miura
Keyword(s):  
Mechanical Properties ◽  
Residual Stress ◽  
Thermal Deformation ◽  
Flip Chip ◽  
Flexural Rigidity ◽  
Three Dimensional ◽  
Strain Gauges ◽  
Copper Interconnection ◽  
Induced Stress ◽  
Alignment Structure

Since the thickness of stacked silicon chips in 3D integration has been thinned to less than 100 μm, the local thermal deformation of the chips has increased drastically because of the decrease of the flexural rigidity of the thinned chips. The clear periodic thermal deformation and thus, the local distribution of thermal residual stress appears in the stacked chips due to the periodic alignment of metallic bumps, and they sometimes deteriorate mechanical and electrical reliability of electronic products. In this paper, the dominant structural factors of the local residual stress in a silicon chip are investigated quantitatively based on the results of a three-dimensional finite element analysis and the measurement of the local residual stress in a chip using stress sensor chips. The piezoresistive strain gauges were embedded in the sensor chips. The length of each gauge was 2 μm, and an unit cell consisted of four gauges with different crystallographic directions. This alignment of the strain gauges enables us to measure the tensor component of three-dimensional stress fields separately. Test flip chip substrates were made of silicon chip on which the area-arrayed tin/copper bumps were electroplated. The width of a bump was fixed at 200 μm, and the bump pitch was varied from 400 μm to 1000 μm. The thickness of the copper bump was about 40 μm and that of tin layer was about 10 μm. This tin layer was used for the formation of rigid joint by alloying it with copper interconnection formed on a stress sensing chip. The measured amplitude of the residual stress increased from about 30 MPa to 250 MPa depending on the combination of materials such as bump, underfill, and interconnections. It was confirmed that both the material constant of underfill and the alignment structure of fine bumps are the dominant factors of the local deformation and stress of a silicon chip mounted on area-arrayed metallic bumps. It was also confirmed that not only the control of mechanical properties of electroplated copper thin films, but also the hound’s-tooth alignment of a through silicon via and a bump are indispensable for minimizing the packaging-induced stress in the three-dimensionally mounted chips. This test chip is very effective for evaluating the packaging-process-induced stress in 3D stacked chips quantitatively.

Numerical analysis of thermal deformation and residual stress for selective laser melting process

2016 ◽  
Vol 2016.24 (0) ◽  
pp. 431
Author(s):  
Ryo AKAMATSU ◽  
Toshi-Taka IKESHOJI ◽  
Masahiro ARAKI ◽  
Makiko YONEHARA ◽  
Kazuya NAMAMURA ◽  
...  
Keyword(s):  
Residual Stress ◽  
Numerical Analysis ◽  
Selective Laser Melting ◽  
Thermal Deformation ◽  
Melting Process ◽  
Laser Melting ◽  
Selective Laser Melting Process

Analysis of Welding Process for Automotive Rear Cradle

2015 ◽  
Vol 1091 ◽  
pp. 97-101
Author(s):  
Hak Jae Seol ◽  
Kyoung Teak Lee ◽  
Chang Soo Park ◽  
Kwan Bong Yoo
Keyword(s):  
Residual Stress ◽  
Phase Transformation ◽  
Temperature Distribution ◽  
Transformation Temperature ◽  
Thermal Deformation ◽  
Welding Process ◽  
Phase Transformation Temperature ◽  
Side Member ◽  
Cross Member ◽  
Total Model

A rear cradle as one of the suspension system takes a role to connect a tie rod, suspension arm, transmissions and rubber bush. It consists of the side member and cross member which are joined by welding process. However, the rear cradle may be distorted due to thermal deformation during welding process, which cause dimensional tolerance problem when assembling. So, it is necessary to predict the thermal deformation and the optimal welding conditions should be suggested to reduce the dimensional tolerances. In this paper, MAG(metal active gas) welding process was applied in the simulation model using the SYSWELDR, commercial S/W for welding simulation. And then, It should be predicted on the results about the gap and thermal deformation of main cylinder and derived the phase transformation, temperature distribution, residual stress and thermal deformation of total model shape.

Measurement of the local residual stress between fine metallic bumps in 3D flip chip structures

2014 ◽  
Vol 8 (1/2/3) ◽  
pp. 21 ◽  
Author(s):  
Kota Nakahira ◽  
Hironori Tago ◽  
Takuya Sasaki ◽  
Ken Suzuki ◽  
Hideo Miura
Keyword(s):  
Residual Stress ◽  
Flip Chip
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