CPAM: a common power analysis methodology for high-performance VLSI design

2002 ◽  
Author(s):  
J.S. Neely ◽  
H.H. Chen ◽  
S.G. Walker ◽  
J. Venuto ◽  
T.J. Bucelot
Keyword(s):  
Power Analysis ◽  
High Performance ◽  
Vlsi Design ◽  
Analysis Methodology

scholarly journals A HIGH-PERFORMANCE AND LOW-POWER DELAY BUFFER

2013 ◽  
pp. 78-82
Author(s):  
GOPALA KRISHNA.M ◽  
UMA SANKAR.CH ◽  
NEELIMA. S ◽  
KOTESWARA RAO.P
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Vlsi Design ◽  
Flip Flop ◽  
Ring Counter ◽  
Double Edge ◽  
Low Power Cmos ◽  
Cmos Vlsi

In this paper, presents circuit design of a low-power delay buffer. The proposed delay buffer uses several new techniques to reduce its power consumption. Since delay buffers are accessed sequentially, it adopts a ring-counter addressing scheme. In the ring counter, double-edge-triggered (DET) flip-flops are utilized to reduce the operating frequency by half and the C-element gated-clock strategy is proposed. Both total transistor count and the number of clocked transistors are significantly reduced to improve power consumption and speed in the flip-flop. The number of transistors is reduced by 56%-60% and the Area-Speed-Power product is reduced by 56%-63% compared to other double edge triggered flip-flops. This design is suitable for high-speed, low-power CMOS VLSI design applications.

scholarly journals A Glitch-Free Novel DET-FF in 22 nm CMOS for Low-Power Application

2018 ◽  
Vol 2018 ◽  
pp. 1-6 ◽  
Author(s):  
Sumitra Singar ◽  
N. K. Joshi ◽  
P. K. Ghosh
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Performance ◽  
Vlsi Design ◽  
Total System ◽  
Clock Frequency ◽  
Flip Flop ◽  
Digital Vlsi ◽  
Feedback Structure ◽  
Power Application

Dual edge triggered (DET) techniques are most liked choice for the researchers in the field of digital VLSI design because of its high-performance and low-power consumption standard. Dual edge triggered techniques give the similar throughput at half of the clock frequency as compared to the single edge triggered (SET) techniques. Dual edge triggered techniques can reduce the 50% power consumption and increase the total system power savings. The low-power glitch-free novel dual edge triggered flip-flop (DET-FF) design is proposed in this paper. Still now, existing DET-FF designs are constructed by using either C-element circuit or 1P-2N structure or 2P-1N structure, but the proposed novel design is designed by using the combination of C-element circuit and 2P-1N structure. In this design, if any glitch affects one of the structures, then it is nullified by the other structure. To control the input loading, the two circuits are merged to share the transistors connected to the input. In the proposed design, we have used an internal dual feedback structure. The proposed design reduces the delay and power consumption and increases the speed and efficiency of the system.

Combinational Counters: A Low Overhead Approach to Address DPA Attacks

2019 ◽  
Vol 29 (06) ◽  
pp. 2050097
Author(s):  
Ghobad Zarrinchian ◽  
Morteza Saheb Zamani
Keyword(s):  
Low Power ◽  
Power Analysis ◽  
High Performance ◽  
Clock Cycle ◽  
Experimental Results ◽  
Differential Power Analysis ◽  
Cryptographic Algorithms ◽  
Encryption Algorithms ◽  
And Performance

Differential Power Analysis (DPA) attacks are known as viable and practical techniques to break the security of cryptographic algorithms. In this type of attack, an adversary extracts the encryption key based on the correlation of consumed power of the hardware running encryption algorithms to the processed data. To address DPA attacks in the hardware layer, various techniques have been proposed thus far. However, current techniques generally impose high performance overhead. Especially, the power overhead is a serious issue which may limit the applicability of current techniques in power-constrained applications. In this paper, combinational counters are explored as a way to address the DPA attacks. By randomizing the consumed power in each clock cycle of the circuit operation, these counters can enhance the resistance of the cryptographic cores against DPA attacks with low power overhead as well as zero timing overhead. Experimental results for an AES S-Box module in 45[Formula: see text]nm technology reveal that the proposed technique is capable of achieving higher level of security in comparison to two other approaches while preserving the power and performance overhead at a same or lower level.

Statistical Power Analysis for High-Performance Processors

2009 ◽  
Vol 5 (1) ◽  
pp. 70-76 ◽  
Author(s):  
Howard Chen ◽  
Scott Neely ◽  
Jinjun Xiong ◽  
Vladimir Zolotov ◽  
Chandu Visweswariah
Keyword(s):  
Power Analysis ◽  
Statistical Power ◽  
High Performance ◽  
Statistical Power Analysis
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