Nanotechnology (45 nm) based Low power and High performance 4x4 Multiplier based on Six Transistors (6T) Full Adder & 2T XNOR Gate

2021 ◽  
Author(s):  
Misha Urooj Khan ◽  
Muhammad Zeeshan ◽  
Usama Gulzar ◽  
Muhammad Muneeb ◽  
Zeeshan Abbasi ◽  
...  
Keyword(s):  
Low Power ◽  
High Performance ◽  
Full Adder ◽  
Xnor Gate

Performance Analysis of Various Multipliers Using 8T-full Adder with 180nm Technology

2020 ◽  
Vol 13 (6) ◽  
pp. 864-870
Author(s):  
Sai Venkatramana Prasada G.S ◽  
G. Seshikala ◽  
S. Niranjana
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
High Performance ◽  
Full Adder ◽  
Fundamental Operation ◽  
Wallace Tree ◽  
Power Delay Product ◽  
The Comparative Study ◽  
Wallace Tree Multiplier

Background: This paper presents the comparative study of power dissipation, delay and power delay product (PDP) of different full adders and multiplier designs. Methods: Full adder is the fundamental operation for any processors, DSP architectures and VLSI systems. Here ten different full adder structures were analyzed for their best performance using a Mentor Graphics tool with 180nm technology. Results: From the analysis result high performance full adder is extracted for further higher level designs. 8T full adder exhibits high speed, low power delay and low power delay product and hence it is considered to construct four different multiplier designs, such as Array multiplier, Baugh Wooley multiplier, Braun multiplier and Wallace Tree multiplier. These different structures of multipliers were designed using 8T full adder and simulated using Mentor Graphics tool in a constant W/L aspect ratio. Conclusion: From the analysis, it is concluded that Wallace Tree multiplier is the high speed multiplier but dissipates comparatively high power. Baugh Wooley multiplier dissipates less power but exhibits more time delay and low PDP.

scholarly journals Novel Design of Low-Power High-Speed Hybrid Full Adder Design using Gate Diffusion Input (GDI) Technique

2020 ◽  
Vol 9 (12) ◽  
pp. 323-328
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Critical Path ◽  
Circuit Simulation ◽  
Full Adder ◽  
Cmos Process ◽  
Path Delay ◽  
Process Technology ◽  
Xnor Gate

VLSI technology become one of the most significant and demandable because of the characteristics like device portability, device size, large amount of features, expenditure, consistency, rapidity and many others. Multipliers and Adders place an important role in various digital systems such as computers, process controllers and signal processors in order to achieve high speed and low power. Two input XOR/XNOR gate and 2:1 multiplexer modules are used to design the Hybrid Full adders. The XOR/XNOR gate is the key punter of power included in the Full adder cell. However this circuit increases the delay, area and critical path delay. Hence, the optimum design of the XOR/XNOR is required to reduce the power consumption of the Full adder Cell. So a 6 New Hybrid Full adder circuits are proposed based on the Novel Full-Swing XOR/XNOR gates and a New Gate Diffusion Input (GDI) design of Full adder with high-swing outputs. The speed, power consumption, power delay product and driving capability are the merits of the each proposed circuits. This circuit simulation was carried used cadence virtuoso EDA tool. The simulation results based on the 90nm CMOS process technology model.

Low-Power and High-Performance 1-Bit CMOS Full-Adder Cell

2008 ◽  
Vol 3 (2) ◽  
Author(s):  
Keivan Navi ◽  
Omid Kavehei ◽  
Mahnoush Rouholamini ◽  
Amir Sahafi ◽  
Shima Mehrabi ◽  
...  
Keyword(s):  
Low Power ◽  
High Performance ◽  
Full Adder

Mixed Full Adder topologies for high-performance low-power arithmetic circuits

2007 ◽  
Vol 38 (1) ◽  
pp. 130-139 ◽  
Author(s):  
M. Alioto ◽  
G. Di Cataldo ◽  
G. Palumbo
Keyword(s):  
Low Power ◽  
High Performance ◽  
Full Adder ◽  
Arithmetic Circuits

DESIGN AND ANALYSIS OF A NOVEL LOW PDP FULL ADDER CELL

2011 ◽  
Vol 20 (03) ◽  
pp. 439-445 ◽  
Author(s):  
M. H. GHADIRY ◽  
ABU KHARI A'AIN ◽  
M. NADI S.
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Performance ◽  
Full Adder ◽  
Cmos Technology ◽  
Accurate Analysis ◽  
And Performance ◽  
Full Swing ◽  
Driving Capability

This paper, presents a new full-swing low power high performance full adder circuit in CMOS technology. It benefits from a full swing XOR-XNOR module with no feedback transistors, which decreases delay and power consumption. In addition, high driving capability of COUT module and low PDP design of SUM module contribute to more PDP reduction in cascaded mode. In order to have accurate analysis, the new circuit along with several well-known full adders from literature have been modeled and compared with CADENCE. Comparison consists of power consumption, performance, PDP, and area. Results show that there are improvements in both power consumption and performance. This design trades area with low PDP.

scholarly journals Forced stack sleep transistor (FORTRAN): A new leakage current reduction approach in CMOS based circuit designing

2021 ◽  
Vol 34 (2) ◽  
pp. 259-280
Author(s):  
Sankit Kassa ◽  
Neeraj Misra ◽  
Rajendra Nagaria
Keyword(s):  
Low Power ◽  
Leakage Current ◽  
Power Efficiency ◽  
High Performance ◽  
Low Voltage ◽  
Full Adder ◽  
Leakage Power ◽  
Modes Of Operation ◽  
Power Circuit ◽  
Current Reduction

Reduction in leakage current has become a significant concern in nanotechnology-based low-power, low-voltage, and high-performance VLSI applications. This research article discusses a new low-power circuit design the approach of FORTRAN (FORced stack sleep TRANsistor), which decreases the leakage power efficiency in the CMOS-based circuit outline in VLSI domain. FORTRAN approach reduces leakage current in both active as well as standby modes of operation. Furthermore, it is not time intensive when the circuit goes from active mode to standby mode and vice-versa. To validate the proposed design approach, experiments are conducted in the Tanner EDA tool of mentor graphics bundle on projected circuit designs for the full adder, a chain of 4-inverters, and 4- bit multiplier designs utilizing 180nm, 130nm, and 90nm TSMC technology node. The outcomes obtained show the result of a 95-98% vital reduction in leakage power as well as a 15-20% reduction in dynamic power with a minor increase in delay. The result outcomes are compared for accuracy with the notable design approaches that are accessible for both active and standby modes of operation.

Low power and high performance dynamic CMOS XOR/XNOR gate design

2011 ◽  
Vol 88 (8) ◽  
pp. 2781-2784 ◽  
Author(s):  
Jinhui Wang ◽  
Na Gong ◽  
Ligang Hou ◽  
Xiaohong Peng ◽  
Shuqin Geng ◽  
...  
Keyword(s):  
Low Power ◽  
High Performance ◽  
Xnor Gate ◽  
Gate Design
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