Low-Cost and Fast Hardware Implementations of Point Multiplication on Binary Edwards Curves

2018 ◽  
Author(s):  
Bahram Rashidi
Keyword(s):  
Low Cost ◽  
Point Multiplication ◽  
Edwards Curves ◽  
Hardware Implementations

Efficient Lightweight Hardware Structures of Point Multiplication on Binary Edwards Curves for Elliptic Curve Cryptosystems

2019 ◽  
Vol 28 (09) ◽  
pp. 1950149
Author(s):  
Bahram Rashidi ◽  
Mohammad Abedini
Keyword(s):  
High Speed ◽  
Critical Path ◽  
Low Cost ◽  
Path Delay ◽  
Point Multiplication ◽  
Low Area ◽  
Elliptic Curve Cryptosystems ◽  
Edwards Curves ◽  
Special Cases ◽  
Field Multiplication

This paper presents efficient lightweight hardware implementations of the complete point multiplication on binary Edwards curves (BECs). The implementations are based on general and special cases of binary Edwards curves. The complete differential addition formulas have the cost of [Formula: see text] and [Formula: see text] for general and special cases of BECs, respectively, where [Formula: see text] and [Formula: see text] denote the costs of a field multiplication, a field squaring and a field multiplication by a constant, respectively. In the general case of BECs, the structure is implemented based on 3 concurrent multipliers. Also in the special case of BECs, two structures by employing 3 and 2 field multipliers are proposed for achieving the highest degree of parallelization and utilization of resources, respectively. The field multipliers are implemented based on the proposed efficient digit–digit polynomial basis multiplier. Two input operands of the multiplier proceed in digit level. This property leads to reduce hardware consumption and critical path delay. Also, in the structure, based on the change of input digit size from low digit size to high digit size the number of clock cycles and input words are different. Therefore, the multiplier can be flexible for different cryptographic considerations such as low-area and high-speed implementations. The point multiplication computation requires field inversion, therefore, we use a low-cost Extended Euclidean Algorithm (EEA) based inversion for implementation of this field operation. Implementation results of the proposed architectures based on Virtex-5 XC5VLX110 FPGA for two fields [Formula: see text] and [Formula: see text] are achieved. The results show improvements in terms of area and efficiency for the proposed structures compared to previous works.

scholarly journals Low-Cost, Low-Power FPGA Implementation of ED25519 and CURVE25519 Point Multiplication

Information ◽  
2019 ◽  
Vol 10 (9) ◽  
pp. 285 ◽  
Author(s):  
Mohamad Ali Mehrabi ◽  
Christophe Doche
Keyword(s):  
Low Power ◽  
Low Cost ◽  
Fpga Implementation ◽  
Large Integer ◽  
Modular Multiplication ◽  
Point Multiplication ◽  
Low Area ◽  
Edwards Curves ◽  
Digital Signature Algorithm ◽  
Edwards Curve

Twisted Edwards curves have been at the center of attention since their introduction by Bernstein et al. in 2007. The curve ED25519, used for Edwards-curve Digital Signature Algorithm (EdDSA), provides faster digital signatures than existing schemes without sacrificing security. The CURVE25519 is a Montgomery curve that is closely related to ED25519. It provides a simple, constant time, and fast point multiplication, which is used by the key exchange protocol X25519. Software implementations of EdDSA and X25519 are used in many web-based PC and Mobile applications. In this paper, we introduce a low-power, low-area FPGA implementation of the ED25519 and CURVE25519 scalar multiplication that is particularly relevant for Internet of Things (IoT) applications. The efficiency of the arithmetic modulo the prime number 2 255 - 19 , in particular the modular reduction and modular multiplication, are key to the efficiency of both EdDSA and X25519. To reduce the complexity of the hardware implementation, we propose a high-radix interleaved modular multiplication algorithm. One benefit of this architecture is to avoid the use of large-integer multipliers relying on FPGA DSP modules.

scholarly journals A Compact Coprocessor for the Elliptic Curve Point Multiplication over Gaussian Integers

Electronics ◽  
2020 ◽  
Vol 9 (12) ◽  
pp. 2050
Author(s):  
Malek Safieh ◽  
Johann-Philipp Thiers ◽  
Jürgen Freudenberger
Keyword(s):  
Elliptic Curve ◽  
Modular Arithmetic ◽  
Complex Numbers ◽  
Gaussian Integer ◽  
Gaussian Integers ◽  
Point Multiplication ◽  
Hardware Implementations ◽  
Secure Hardware ◽  
Prime Fields ◽  
High Flexibility

This work presents a new concept to implement the elliptic curve point multiplication (PM). This computation is based on a new modular arithmetic over Gaussian integer fields. Gaussian integers are a subset of the complex numbers such that the real and imaginary parts are integers. Since Gaussian integer fields are isomorphic to prime fields, this arithmetic is suitable for many elliptic curves. Representing the key by a Gaussian integer expansion is beneficial to reduce the computational complexity and the memory requirements of secure hardware implementations, which are robust against attacks. Furthermore, an area-efficient coprocessor design is proposed with an arithmetic unit that enables Montgomery modular arithmetic over Gaussian integers. The proposed architecture and the new arithmetic provide high flexibility, i.e., binary and non-binary key expansions as well as protected and unprotected PM calculations are supported. The proposed coprocessor is a competitive solution for a compact ECC processor suitable for applications in small embedded systems.

scholarly journals A Low Cost Carbon Nanofiber Based Spiral Inductor: Inference and Implementation

2014 ◽  
Vol 2014 ◽  
pp. 1-8 ◽  
Author(s):  
John Wiselin ◽  
Sreeja Balakrishnapillai Suseela ◽  
Bycil Viswambaran Jalaja ◽  
Sherin Dhas Sahayadas Padma Ramani ◽  
Rajesh Prasad ◽  
...  
Keyword(s):  
Carbon Fiber ◽  
Quality Factor ◽  
Carbon Fibers ◽  
Carbon Nanofiber ◽  
Low Cost ◽  
Simulation Software ◽  
Spiral Inductor ◽  
Hardware Implementations

This paper investigates the possibilities of using carbon fiber as an inductor material by analyzing its inductive properties. Various shapes such as rectangular, spiral, helical, and cylindrical line structures have been simulated under various constraints using simulation software. Hardware implementations were also tested and both simulation and hardware results show that carbon fibers have the potential to replace copper inductor lines. The implemented spiral inductor produced a quality factor of 40 while producing an inductance of 4 nH at 1.2 GHz frequency.

NEW BINARY MORPHOLOGICAL OPERATIONS FOR EFFECTIVE LOW-COST BOUNDARY DETECTION

2003 ◽  
Vol 17 (02) ◽  
pp. 201-213 ◽  
Author(s):  
AISHY AMER
Keyword(s):  
Hardware Implementation ◽  
Low Cost ◽  
Boundary Detection ◽  
Morphological Operations ◽  
Binary Images ◽  
Detection Algorithms ◽  
Boundary Points ◽  
Hardware Implementations ◽  
Gradient Based

In this paper, new operational definitions of binary morphological, both conditional and nonconditional, operations are proposed. The new operations are applied to detect boundary points from binary images. Comparisons of boundary detection algorithms using proposed, standard morphological, and gradient-based operations, showing the effectiveness of the proposed operations, are given. Comparative hardware implementations of standard and proposed morphological operations are also given. Main distinguishing aspects of the new operations are: speed and low hardware implementation (i.e., e.g., low number of buffers and D-Flip–Flops).

scholarly journals Low-cost portable TRNG, implementation and evaluation

2016 ◽  
Vol 13 (3) ◽  
pp. 361-368
Author(s):  
Igor Fermevc ◽  
Sasa Adamovic
Keyword(s):  
Integrated Circuit ◽  
Low Cost ◽  
Random Sequence ◽  
Noise Signal ◽  
Statistical Characteristics ◽  
End User ◽  
High Entropy ◽  
Work Related ◽  
Hardware Implementations

This paper will show one of many possible hardware implementations of random sequence generators and give a short survey on existing work related to techniques used for producing true random bits. By using cheap electronic components found in every specialized store such as 8-bit RISC microcontroler, double analogue comparator chip and USB to RS232 interface integrated circuit, we were able to produce a low cost, higly portable device that outputs random sequences with excellent statistical characteristics and high entropy. The source of randomness is a mix of techniques such as electronic noise, phase noise and oscillator jitter. The device in question has a built-in debiasing algorithm similar to [1] and a security mechanism that protects the end user by constantly monitoring the quality of digitized noise signal. Finaly, we will show the results of comparative analysis of data acquired from our device and ?random.org? online service.

scholarly journals An Efficient, Low-Cost Routing Architecture for Spiking Neural Network Hardware Implementations

2018 ◽  
Vol 48 (3) ◽  
pp. 1777-1788 ◽  
Author(s):  
Yuling Luo ◽  
Lei Wan ◽  
Junxiu Liu ◽  
Jim Harkin ◽  
Yi Cao
Keyword(s):  
Neural Network ◽  
Low Cost ◽  
Spiking Neural Network ◽  
Hardware Implementations ◽  
Neural Network Hardware

scholarly journals A Hidden DCT-Based Invisible Watermarking Method for Low-Cost Hardware Implementations

Electronics ◽  
2021 ◽  
Vol 10 (12) ◽  
pp. 1465
Author(s):  
Yuxuan Wang ◽  
Yuanyong Luo ◽  
Zhongfeng Wang ◽  
Hongbing Pan
Keyword(s):  
Resource Sharing ◽  
Power Efficiency ◽  
High Speed ◽  
Low Cost ◽  
Color Space ◽  
Computational Cost ◽  
Cmos Technology ◽  
Hardware Implementations ◽  
Invisible Watermarking ◽  
Speed Performance

This paper presents an invisible and robust watermarking method and its hardware implementation. The proposed architecture is based on the discrete cosine transform (DCT) algorithm. Novel techniques are applied as well to reduce the computational cost of DCT and color space conversion to achieve low-cost and high-speed performance. Besides, a watermark embedder and a blind extractor are implemented in the same circuit using a resource-sharing method. Our approach is compatible with various watermarking embedding ratios, such as 1/16 and 1/64, with a PSNR of over 45 and the NC value of 1. After Joint Photographic Experts Group (JPEG) compression with a quality factor (QF) of 50, our method can achieve an NC value of 0.99. Results from a design compiler (DC) with TSMC-90 nm CMOS technology show that our design can achieve the frequency of 2.32 GHz with the area consumption of 304,980.08 μm2 and power consumption of 508.1835 mW. For the FPGA implementation, our method achieved a frequency of 421.94 MHz. Compared with the state-of-the-art works, our design improved the frequency by 4.26 times, saved 90.2% on area and increased the power efficiency by more than 1000 fold.

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