Efficient hardware implementations of point multiplication for binary Edwards curves

2018 ◽  
Vol 46 (8) ◽  
pp. 1516-1533 ◽  
Author(s):  
Bahram Rashidi
Keyword(s):  
Point Multiplication ◽  
Edwards Curves ◽  
Hardware Implementations

Efficient Lightweight Hardware Structures of Point Multiplication on Binary Edwards Curves for Elliptic Curve Cryptosystems

2019 ◽  
Vol 28 (09) ◽  
pp. 1950149
Author(s):  
Bahram Rashidi ◽  
Mohammad Abedini
Keyword(s):  
High Speed ◽  
Critical Path ◽  
Low Cost ◽  
Path Delay ◽  
Point Multiplication ◽  
Low Area ◽  
Elliptic Curve Cryptosystems ◽  
Edwards Curves ◽  
Special Cases ◽  
Field Multiplication

This paper presents efficient lightweight hardware implementations of the complete point multiplication on binary Edwards curves (BECs). The implementations are based on general and special cases of binary Edwards curves. The complete differential addition formulas have the cost of [Formula: see text] and [Formula: see text] for general and special cases of BECs, respectively, where [Formula: see text] and [Formula: see text] denote the costs of a field multiplication, a field squaring and a field multiplication by a constant, respectively. In the general case of BECs, the structure is implemented based on 3 concurrent multipliers. Also in the special case of BECs, two structures by employing 3 and 2 field multipliers are proposed for achieving the highest degree of parallelization and utilization of resources, respectively. The field multipliers are implemented based on the proposed efficient digit–digit polynomial basis multiplier. Two input operands of the multiplier proceed in digit level. This property leads to reduce hardware consumption and critical path delay. Also, in the structure, based on the change of input digit size from low digit size to high digit size the number of clock cycles and input words are different. Therefore, the multiplier can be flexible for different cryptographic considerations such as low-area and high-speed implementations. The point multiplication computation requires field inversion, therefore, we use a low-cost Extended Euclidean Algorithm (EEA) based inversion for implementation of this field operation. Implementation results of the proposed architectures based on Virtex-5 XC5VLX110 FPGA for two fields [Formula: see text] and [Formula: see text] are achieved. The results show improvements in terms of area and efficiency for the proposed structures compared to previous works.

scholarly journals A Compact Coprocessor for the Elliptic Curve Point Multiplication over Gaussian Integers

Electronics ◽  
2020 ◽  
Vol 9 (12) ◽  
pp. 2050
Author(s):  
Malek Safieh ◽  
Johann-Philipp Thiers ◽  
Jürgen Freudenberger
Keyword(s):  
Elliptic Curve ◽  
Modular Arithmetic ◽  
Complex Numbers ◽  
Gaussian Integer ◽  
Gaussian Integers ◽  
Point Multiplication ◽  
Hardware Implementations ◽  
Secure Hardware ◽  
Prime Fields ◽  
High Flexibility

This work presents a new concept to implement the elliptic curve point multiplication (PM). This computation is based on a new modular arithmetic over Gaussian integer fields. Gaussian integers are a subset of the complex numbers such that the real and imaginary parts are integers. Since Gaussian integer fields are isomorphic to prime fields, this arithmetic is suitable for many elliptic curves. Representing the key by a Gaussian integer expansion is beneficial to reduce the computational complexity and the memory requirements of secure hardware implementations, which are robust against attacks. Furthermore, an area-efficient coprocessor design is proposed with an arithmetic unit that enables Montgomery modular arithmetic over Gaussian integers. The proposed architecture and the new arithmetic provide high flexibility, i.e., binary and non-binary key expansions as well as protected and unprotected PM calculations are supported. The proposed coprocessor is a competitive solution for a compact ECC processor suitable for applications in small embedded systems.

scholarly journals Low-Cost, Low-Power FPGA Implementation of ED25519 and CURVE25519 Point Multiplication

Information ◽  
2019 ◽  
Vol 10 (9) ◽  
pp. 285 ◽  
Author(s):  
Mohamad Ali Mehrabi ◽  
Christophe Doche
Keyword(s):  
Low Power ◽  
Low Cost ◽  
Fpga Implementation ◽  
Large Integer ◽  
Modular Multiplication ◽  
Point Multiplication ◽  
Low Area ◽  
Edwards Curves ◽  
Digital Signature Algorithm ◽  
Edwards Curve

Twisted Edwards curves have been at the center of attention since their introduction by Bernstein et al. in 2007. The curve ED25519, used for Edwards-curve Digital Signature Algorithm (EdDSA), provides faster digital signatures than existing schemes without sacrificing security. The CURVE25519 is a Montgomery curve that is closely related to ED25519. It provides a simple, constant time, and fast point multiplication, which is used by the key exchange protocol X25519. Software implementations of EdDSA and X25519 are used in many web-based PC and Mobile applications. In this paper, we introduce a low-power, low-area FPGA implementation of the ED25519 and CURVE25519 scalar multiplication that is particularly relevant for Internet of Things (IoT) applications. The efficiency of the arithmetic modulo the prime number 2 255 - 19 , in particular the modular reduction and modular multiplication, are key to the efficiency of both EdDSA and X25519. To reduce the complexity of the hardware implementation, we propose a high-radix interleaved modular multiplication algorithm. One benefit of this architecture is to avoid the use of large-integer multipliers relying on FPGA DSP modules.

scholarly journals Flexible and Transparent Memristive Synapse Based on Polyvinylpyrrolidone/N-doped Carbon Quantum Dot Nanocomposites for Neuromorphic Computing

2021 ◽  
Author(s):  
Tao Zeng ◽  
Zhi Yang ◽  
Jiabing Liang ◽  
Ya Lin ◽  
Yankun Cheng ◽  
...  
Keyword(s):  
Quantum Dot ◽  
Neuromorphic Computing ◽  
Carbon Quantum Dot ◽  
Hardware Implementations

Memristive devices are widely recognized as promising hardware implementations of neuromorphic computing. Herein, a flexible and transparent memristive synapse based on polyvinylpyrrolidone (PVP)/N-doped carbon quantum dot (NCQD) nanocomposites through regulating...

EXPRESS: Design Considerations for Discrete Frequency Infrared Microscopy Systems

2021 ◽  
pp. 000370282110133
Author(s):  
Rohit Bhargava ◽  
Yamuna Dilip Phal ◽  
Kevin Yeh
Keyword(s):  
Imaging System ◽  
Chemical Imaging ◽  
Optical Component ◽  
Imaging Systems ◽  
Imaging Data ◽  
Discrete Frequency ◽  
Figures Of Merit ◽  
Design Considerations ◽  
Hardware Implementations ◽  
Measurement Capabilities

Discrete frequency infrared (DFIR) chemical imaging is transforming the practice of microspectroscopy by enabling a diversity of instrumentation and new measurement capabilities. While a variety of hardware implementations have been realized, considerations in the design of all-IR microscopes have not yet been compiled. Here we describe the evolution of IR microscopes, provide rationales for design choices, and the major considerations for each optical component that together comprise an imaging system. We analyze design choices in illustrative examples that use these components to optimize performance, under their particular constraints. We then summarize a framework to assess the factors that determine an instrument’s performance mathematically. Finally, we summarize the design and analysis approach by enumerating performance figures of merit for spectroscopic imaging data that can be used to evaluate the capabilities of imaging systems or suitability for specific intended applications. Together, the presented concepts and examples should aid in understanding available instrument configurations, while guiding innovations in design of the next generation of IR chemical imaging spectrometers.

scholarly journals A Review of Algorithms and Hardware Implementations for Spiking Neural Networks

2021 ◽  
Vol 11 (2) ◽  
pp. 23
Author(s):  
Duy-Anh Nguyen ◽  
Xuan-Tu Tran ◽  
Francesca Iacopi
Keyword(s):  
Neural Networks ◽  
Computational Cost ◽  
Superior Performance ◽  
Training Algorithms ◽  
Current State ◽  
Hardware Implementations ◽  
Neuromorphic Hardware ◽  
High Level ◽  
Event Based ◽  
Hardware Platforms

Deep Learning (DL) has contributed to the success of many applications in recent years. The applications range from simple ones such as recognizing tiny images or simple speech patterns to ones with a high level of complexity such as playing the game of Go. However, this superior performance comes at a high computational cost, which made porting DL applications to conventional hardware platforms a challenging task. Many approaches have been investigated, and Spiking Neural Network (SNN) is one of the promising candidates. SNN is the third generation of Artificial Neural Networks (ANNs), where each neuron in the network uses discrete spikes to communicate in an event-based manner. SNNs have the potential advantage of achieving better energy efficiency than their ANN counterparts. While generally there will be a loss of accuracy on SNN models, new algorithms have helped to close the accuracy gap. For hardware implementations, SNNs have attracted much attention in the neuromorphic hardware research community. In this work, we review the basic background of SNNs, the current state and challenges of the training algorithms for SNNs and the current implementations of SNNs on various hardware platforms.

Power Side-Channel Analysis of RNS GLV ECC Using Machine and Deep Learning Algorithms

2021 ◽  
Vol 21 (3) ◽  
pp. 1-20
Author(s):  
Mohamad Ali Mehrabi ◽  
Naila Mukhtar ◽  
Alireza Jolfaei
Keyword(s):  
Deep Learning ◽  
Elliptic Curve ◽  
Smart Cities ◽  
Information Leakage ◽  
Side Channel ◽  
Side Channel Attacks ◽  
Public Key Cryptosystems ◽  
Elliptic Curve Cryptosystems ◽  
Hardware Implementations ◽  
Substantial Progress

Many Internet of Things applications in smart cities use elliptic-curve cryptosystems due to their efficiency compared to other well-known public-key cryptosystems such as RSA. One of the important components of an elliptic-curve-based cryptosystem is the elliptic-curve point multiplication which has been shown to be vulnerable to various types of side-channel attacks. Recently, substantial progress has been made in applying deep learning to side-channel attacks. Conceptually, the idea is to monitor a core while it is running encryption for information leakage of a certain kind, for example, power consumption. The knowledge of the underlying encryption algorithm can be used to train a model to recognise the key used for encryption. The model is then applied to traces gathered from the crypto core in order to recover the encryption key. In this article, we propose an RNS GLV elliptic curve cryptography core which is immune to machine learning and deep learning based side-channel attacks. The experimental analysis confirms the proposed crypto core does not leak any information about the private key and therefore it is suitable for hardware implementations.

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