Surface activation process of lead-free solder bumps for low temperature bonding

Author(s):  
YingHui Wang ◽  
K. Nishida ◽  
M. Hutter ◽  
M.R. Howlader ◽  
E. Higurashi ◽  
...  
2019 ◽  
Vol 115 (12) ◽  
pp. 122102 ◽  
Author(s):  
Wenhua Yang ◽  
Jie Zhou ◽  
Xinyuan Jiang ◽  
Ximing Ye ◽  
Xiaofeng Xuan ◽  
...  

2015 ◽  
Vol 772 ◽  
pp. 284-289 ◽  
Author(s):  
Sabuj Mallik ◽  
Jude Njoku ◽  
Gabriel Takyi

Voiding in solder joints poses a serious reliability concern for electronic products. The aim of this research was to quantify the void formation in lead-free solder joints through X-ray inspections. Experiments were designed to investigate how void formation is affected by solder bump size and shape, differences in reflow time and temperature, and differences in solder paste formulation. Four different lead-free solder paste samples were used to produce solder bumps on a number of test boards, using surface mount reflow soldering process. Using an advanced X-ray inspection system void percentages were measured for three different size and shape solder bumps. Results indicate that the voiding in solder joint is strongly influenced by solder bump size and shape, with voids found to have increased when bump size decreased. A longer soaking period during reflow stage has negatively affectedsolder voids. Voiding was also accelerated with smaller solder particles in solder paste.


2015 ◽  
Vol 2015 (1) ◽  
pp. 000799-000805
Author(s):  
Marek Gorywoda ◽  
Rainer Dohle ◽  
Bernd Kandler ◽  
Bernd Burger

Electromigration comprises one of the processes affecting the long-term reliability of electronic devices; it has therefore been the focus of many investigations in recent years. In regards to flip chip packaging technology, the majority of published data is concerned with electromigration in solder connections to metallized organic substrates. Hardly any information is available in the literature on electromigration in lead-free solder connections on thin film ceramic substrates. This work presents results of a study of electromigration in lead-free (SAC305) flip chip solder bumps with a nominal diameter of 40 μm or 30 μm with a pitch of 100 μm on silicon chips assembled onto thin film Al2O3 ceramic substrates. The under bump metallization (UBM) comprised of a 5 μm thick electroless nickel immersion gold (ENIG) layer directly deposited on the AlCu0.5 trace. The ceramic substrates were metallized using a thin film multilayer (NiCr-Au(1.5 μm)-Ni(2 μm) structure on the top of which wettable areas were produced with high precision by depositing flash Au (60 nm) of the required diameter (40 μm or 30 μm). All electromigration tests were performed at the temperature of 125 °C. Initially, one chip assembly with 40 μm and one with 30 μm solder bumps was loaded with the current density of 8 kA/cm2 for 1,000 h. The assemblies did not fail and an investigation with SEM revealed no significant changes to the microstructure of the bumps. Thereafter seven chip assemblies with 40 μm solder bumps and five assemblies with 30 μm bumps were subjected to electromigration tests of 14 kA/cm2 or 25 kA/cm2, respectively. Six of the 40 μm-assemblies failed after 7,000 h and none of the 30 μm-assemblies failed after 2,500 h of test duration so far. Investigation of failed samples performed with SEM and EDX showed asymmetric changes of microstructure in respect to current flow. Several intermetallic phases were found to form in the solder. The predominant damage of the interconnects was found to occur at the cathode contact to chip; the Ni-P layers there showed typical columnar Kirkendall voids caused by migration of Ni from the layers into the solder. Failure of the contacts apparently occurred at the interface between Ni-P and solder. In summary, the results of the study indicate a very high stability of lead-free solder connections on ceramic substrates against electromigration. This high stability is primarily due to a better heat dissipation and thus to a relatively low temperature increase of the ceramic packages caused by resistive heating during flow of electric current. In addition, the type of the metallization used in the study seems to be more resistant to electromigration than the standard PCB metallization as it does not contain a copper layer.


2020 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Guang Ren ◽  
Maurice Collins

Purpose This paper aims to investigate the creep behaviour of the recently developed Sn–8Zn–3Bi–xSb (x = 0, 0.5, 1.0 and 1.5) low temperature lead-free solder alloys. Design/methodology/approach An in-house compressive test rig was developed to perform creep tests under stresses of 20–40 MPa and temperature range 25°C–75 °C. Dorn power law and Garofalo hyperbolic sine law were used to model the secondary creep rate. Findings High coefficient of determination R2 of 0.99 is achieved for both the models. It was found that the activation energy of Sn–8Zn–3Bi solder alloy can be significantly increased with addition of Sb, by 60% to 90 kJ/mol approximately, whereas the secondary creep exponent falls in the range 3–7. Improved creep resistance is attributed to solid solution strengthening introduced by micro-alloying. Creep mechanisms that govern the deformation of these newly developed lead-free solder alloys have also been proposed. Originality/value The findings are expected to fill the gap of knowledge on creep behaviour of these newly developed solder alloys, which are possible alternatives as lead-free interconnecting material in low temperature electronic assembly.


2008 ◽  
Vol 130 (1) ◽  
Author(s):  
Wen-Ren Jong ◽  
Hsin-Chun Tsai ◽  
Hsiu-Tao Chang ◽  
Shu-Hui Peng

In this study, the effects of the temperature cyclic loading on three lead-free solder joints of 96.5Sn–3.5Ag, 95.5Sn–3.8Ag-0.7Cu, and 95.5Sn–3.9Ag-0.6Cu bumped wafer level chip scale package (WLCSP) on printed circuit board assemblies are investigated by Taguchi method. The orthogonal arrays of L16 is applied to examine the shear strain effects of solder joints under five temperature loading parameters of the temperature ramp rate, the high and low temperature dwells, and the dwell time of both high and low temperatures by means of three simulated analyses of creep, plastic, and plastic-creep behavior on the WLCSP assemblies. It is found that the temperature dwell is the most significant factor on the effects of shear strain range from these analyses. The effect of high temperature dwell on the shear strain range is larger than that of low temperature dwell in creep analysis, while the effect of high temperature dwell on the shear strain range is smaller than that of low temperature dwell in both plastic and plastic-creep analyses.


2005 ◽  
Vol 128 (3) ◽  
pp. 202-207 ◽  
Author(s):  
Daijiao Wang ◽  
Ronald L. Panton

This paper reports the experimental findings of void formation in eutectic and lead-free solder joints of flip-chip assemblies. A previous theory indicated that the formation of voids is determined by the direction of heating. The experiments were designed to examine the size and location of voids in the solder samples subject to different heat flux directions. A lead-free solder (Sn-3.5Ag-0.75Cu) and a eutectic solder (63Sn37Pb) were employed in the experiments. Previous experiments [Wang, D., and Panton, R. L., 2005, “Experimental Study of Void Formation in High-Lead Solder Joints of Flip-Chip Assemblies,” ASME J. Electron. Packag., 127(2), pp. 120–126; 2005, “Effect of Reversing Heat Flux Direction During Reflow on Void Formation in High-Lead Solder Bumps,” ASME J. Electron. Packag., 127(4), pp. 440–445] employed a high lead solder. 288 solder bumps were processed for each solder. Both eutectic and lead-free solder have shown fewer voids and much smaller void volume than those for high-lead solder. Compared with lead-free solder, eutectic solder has a slightly lower void volume and a lower percentage of defective bumps. For both eutectic and lead-free solders, irrespective of the cooling direction, heating solder samples from the top shows fewer defective bumps and smaller void volume. No significant effect on void formation for either eutectic or lead-free solder was found via reversing the heat flux direction during cooling. Unlike high-lead solder, small voids in eutectic or lead-free solder comprised 35-88% of the total void volume. The final distribution of voids shows a moderate agreement with thermocapillary theory, indicating the significance of the temperature gradient on the formation of voids.


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