The projection of the incidence of dielectric cracking during chip joining with lead free solder bumps

2016 ◽  
Author(s):  
T. M. Shaw ◽  
X-H Liu ◽  
E. Misra ◽  
D. Questad ◽  
G. Bonilla ◽  
...  
Keyword(s):  
Lead Free ◽  
Lead Free Solder ◽  
Solder Bumps ◽  
Free Solder

Quantitative Evaluation of Voids in Lead Free Solder Joints

2015 ◽  
Vol 772 ◽  
pp. 284-289 ◽  
Author(s):  
Sabuj Mallik ◽  
Jude Njoku ◽  
Gabriel Takyi
Keyword(s):  
Solder Bump ◽  
Solder Joints ◽  
Void Formation ◽  
Lead Free ◽  
Lead Free Solder ◽  
Solder Paste ◽  
X Ray ◽  
Size And Shape ◽  
Solder Bumps ◽  
Free Solder

Voiding in solder joints poses a serious reliability concern for electronic products. The aim of this research was to quantify the void formation in lead-free solder joints through X-ray inspections. Experiments were designed to investigate how void formation is affected by solder bump size and shape, differences in reflow time and temperature, and differences in solder paste formulation. Four different lead-free solder paste samples were used to produce solder bumps on a number of test boards, using surface mount reflow soldering process. Using an advanced X-ray inspection system void percentages were measured for three different size and shape solder bumps. Results indicate that the voiding in solder joint is strongly influenced by solder bump size and shape, with voids found to have increased when bump size decreased. A longer soaking period during reflow stage has negatively affectedsolder voids. Voiding was also accelerated with smaller solder particles in solder paste.

Study on electromigration in flip chip lead-free solder connections with 40 μm or 30 μm diameter on thin film ceramic substrates

2015 ◽  
Vol 2015 (1) ◽  
pp. 000799-000805
Author(s):  
Marek Gorywoda ◽  
Rainer Dohle ◽  
Bernd Kandler ◽  
Bernd Burger
Keyword(s):  
Thin Film ◽  
High Stability ◽  
Flip Chip ◽  
Lead Free ◽  
Published Data ◽  
Organic Substrates ◽  
Lead Free Solder ◽  
Ceramic Substrates ◽  
Solder Bumps ◽  
Free Solder

Electromigration comprises one of the processes affecting the long-term reliability of electronic devices; it has therefore been the focus of many investigations in recent years. In regards to flip chip packaging technology, the majority of published data is concerned with electromigration in solder connections to metallized organic substrates. Hardly any information is available in the literature on electromigration in lead-free solder connections on thin film ceramic substrates. This work presents results of a study of electromigration in lead-free (SAC305) flip chip solder bumps with a nominal diameter of 40 μm or 30 μm with a pitch of 100 μm on silicon chips assembled onto thin film Al2O3 ceramic substrates. The under bump metallization (UBM) comprised of a 5 μm thick electroless nickel immersion gold (ENIG) layer directly deposited on the AlCu0.5 trace. The ceramic substrates were metallized using a thin film multilayer (NiCr-Au(1.5 μm)-Ni(2 μm) structure on the top of which wettable areas were produced with high precision by depositing flash Au (60 nm) of the required diameter (40 μm or 30 μm). All electromigration tests were performed at the temperature of 125 °C. Initially, one chip assembly with 40 μm and one with 30 μm solder bumps was loaded with the current density of 8 kA/cm2 for 1,000 h. The assemblies did not fail and an investigation with SEM revealed no significant changes to the microstructure of the bumps. Thereafter seven chip assemblies with 40 μm solder bumps and five assemblies with 30 μm bumps were subjected to electromigration tests of 14 kA/cm2 or 25 kA/cm2, respectively. Six of the 40 μm-assemblies failed after 7,000 h and none of the 30 μm-assemblies failed after 2,500 h of test duration so far. Investigation of failed samples performed with SEM and EDX showed asymmetric changes of microstructure in respect to current flow. Several intermetallic phases were found to form in the solder. The predominant damage of the interconnects was found to occur at the cathode contact to chip; the Ni-P layers there showed typical columnar Kirkendall voids caused by migration of Ni from the layers into the solder. Failure of the contacts apparently occurred at the interface between Ni-P and solder. In summary, the results of the study indicate a very high stability of lead-free solder connections on ceramic substrates against electromigration. This high stability is primarily due to a better heat dissipation and thus to a relatively low temperature increase of the ceramic packages caused by resistive heating during flow of electric current. In addition, the type of the metallization used in the study seems to be more resistant to electromigration than the standard PCB metallization as it does not contain a copper layer.

Experimental Study of Void Formation in Eutectic and Lead-Free Solder Bumps of Flip-Chip Assemblies

2005 ◽  
Vol 128 (3) ◽  
pp. 202-207 ◽  
Author(s):  
Daijiao Wang ◽  
Ronald L. Panton
Keyword(s):  
Experimental Study ◽  
Heat Flux ◽  
Flip Chip ◽  
Void Formation ◽  
Lead Free ◽  
Void Volume ◽  
Lead Free Solder ◽  
Solder Bumps ◽  
Free Solder ◽  
High Lead

This paper reports the experimental findings of void formation in eutectic and lead-free solder joints of flip-chip assemblies. A previous theory indicated that the formation of voids is determined by the direction of heating. The experiments were designed to examine the size and location of voids in the solder samples subject to different heat flux directions. A lead-free solder (Sn-3.5Ag-0.75Cu) and a eutectic solder (63Sn37Pb) were employed in the experiments. Previous experiments [Wang, D., and Panton, R. L., 2005, “Experimental Study of Void Formation in High-Lead Solder Joints of Flip-Chip Assemblies,” ASME J. Electron. Packag., 127(2), pp. 120–126; 2005, “Effect of Reversing Heat Flux Direction During Reflow on Void Formation in High-Lead Solder Bumps,” ASME J. Electron. Packag., 127(4), pp. 440–445] employed a high lead solder. 288 solder bumps were processed for each solder. Both eutectic and lead-free solder have shown fewer voids and much smaller void volume than those for high-lead solder. Compared with lead-free solder, eutectic solder has a slightly lower void volume and a lower percentage of defective bumps. For both eutectic and lead-free solders, irrespective of the cooling direction, heating solder samples from the top shows fewer defective bumps and smaller void volume. No significant effect on void formation for either eutectic or lead-free solder was found via reversing the heat flux direction during cooling. Unlike high-lead solder, small voids in eutectic or lead-free solder comprised 35-88% of the total void volume. The final distribution of voids shows a moderate agreement with thermocapillary theory, indicating the significance of the temperature gradient on the formation of voids.

Novel flip-chip bonding technology for W-band interconnections using alternate lead-free solder bumps

2002 ◽  
Vol 12 (10) ◽  
pp. 372-374 ◽  
Author(s):  
K. Onodera ◽  
T. Ishii ◽  
S. Aoyama ◽  
S. Sugitani ◽  
M. Tokumitsu
Keyword(s):  
Flip Chip ◽  
Lead Free ◽  
Lead Free Solder ◽  
Flip Chip Bonding ◽  
W Band ◽  
Solder Bumps ◽  
Bonding Technology ◽  
Free Solder

Detection of Poor Wetting of Lead-Free Solder Bumps in Ball Grid Array Packages Using Laser Ultrasound Technique

2011 ◽  
Author(s):  
Jie Gong ◽  
I. Charles Ume
Keyword(s):  
Ball Grid Array ◽  
Lead Free ◽  
Laser Ultrasound ◽  
Lead Free Solder ◽  
Bga Packages ◽  
Solder Bumps ◽  
Out Of Plane ◽  
Free Solder ◽  
Plane Displacement

A novel laser ultrasound and interferometer inspection system has been successfully applied to detect solder joint defects including missing, misaligned, open, and cracked solder bumps in flip chips, land grid array packages and chip capacitors. This system uses a pulsed Nd:YAG laser to induce ultrasound in the chip packages in the thermoelastic regime; it then measures the transient out-of-plane displacement response on the package surface using a laser interferometer. The quality of solder bumps is evaluated by analyzing the transient responses. In this paper, the application of this system is expanded to evaluate quality of lead-free solder bumps in ball grid array (BGA) packages; specifically BGA packages with poor wetting are used as test vehicles. Poor wetting not only decreases the mechanical strength of interconnection at the interface between the solder bumps and substrate, but also increases electrical resistance, which is a reliability issue. Causes of poor wetting vary from materials themselves to manufacturing process. Here, poor wetting of solder bumps were intentionally created by using an improper reflow profile. The transient out-of-plane displacement responses from these packages were compared with the responses from defect-free samples. Solder bumps with poor wetting were distinguished from the normal solder bumps by unusual correlation coefficient. Then, laser ultrasound inspection results are also compared with results from X-ray inspection and continuity test. Finally, the cross-section images were used to further confirm the existence of the poor wetting in samples with unusual correlation coefficient. It can be concluded that this laser-ultrasound system is capable of identifying the presence of poor wetting in BGA packages.

Feasibility Study of a 3D IC Integration System-in-Packaging (SiP) from a 300mm Multi-Project Wafer (MPW)

2011 ◽  
Vol 2011 (1) ◽  
pp. 000446-000454
Author(s):  
J. H. Lau ◽  
C-J Zhan ◽  
P-J Tzeng ◽  
C-K Lee ◽  
M-J Dai ◽  
...  
Keyword(s):  
Printed Circuit Board ◽  
Organic Substrate ◽  
Circuit Board ◽  
Lead Free ◽  
Lead Free Solder ◽  
3D Ic ◽  
Solder Bumps ◽  
Bottom Side ◽  
Free Solder ◽  
Key Enabling Technologies

The feasibility of a 3D IC integration SiP has been demonstrated in this investigation. The heart of this SiP is a TSV (through-silicon via) interposer with RDL (redistribution layer) on both sides, IPD (integrated passive devices) and SS (stress sensors). This interposer is used to support (with microbumps) a stack of four memory chips with TSVs, one thermal chip with heater and one mechanical chip with SS, and then overmolded on its top side for pick and place purposes. The interposer’s bottom-side is attached to an organic substrate (with ordinary lead-free solder bumps), which is lead-free solder-balled on a PCB (printed circuit board). Key enabling technologies such as TSV etching, chemical mechanical polishing (CMP), thin-wafer handling, thermal management, and microbumping, assembly and reliability are highlighted.

Wafer Bumping and Characterizations of Fine-Pitch Lead-Free Solder Microbumps on 12” (300mm) wafer for 3D IC Integration

2011 ◽  
Vol 2011 (1) ◽  
pp. 000650-000656
Author(s):  
J. H. Lau ◽  
P-J Tzeng ◽  
C-K Lee ◽  
C-J Zhan ◽  
M-J Dai ◽  
...  
Keyword(s):  
Cross Sections ◽  
Lead Free ◽  
Lead Free Solder ◽  
Sem Images ◽  
3D Ic ◽  
Fine Pitch ◽  
Solder Bumps ◽  
Before And After ◽  
Free Solder

In this study, the wafer bumping and characterization of fine-pitch lead-free solder microbumps on 300mm wafer for 3D IC integration are investigated. Emphasis is placed on the Cu-plating solutions (conformal and bottom-up). Also, the amount of Cu and solder (Sn) volumes is examined. Furthermore, characterizations such as shearing test and aging of the microbumps are provided and cross sections/SEM images of the microbumps before and after test are discussed. Finally, the process windows of applying the conventional electroplating wafer bumping method of the ordinary solder bumps to the microbumps are also presented.

Void Inspection in Lead-Free Solder Bumps on Ball Grid Array (BGA) Packages Using Laser Ultrasound Technique

2011 ◽  
Author(s):  
Jie Gong ◽  
I. Charles Ume
Keyword(s):  
Ball Grid Array ◽  
Lead Free ◽  
Inspection System ◽  
Laser Ultrasound ◽  
Lead Free Solder ◽  
X Ray ◽  
Bga Packages ◽  
Solder Bumps ◽  
Free Solder ◽  
Ultrasound Inspection

Solder joint voids are usually formed by the entrapped gas bubbles during the reflow process, and are common in all surface mount applications. It is a controversial issue on the reliability of the solder joint, however the consensus is that voiding is acceptable at low contents, while excessive voiding affects mechanical properties, and decreases strength, ductility and fatigue life of the interconnections. X-ray is the most widely used technique to evaluate the voids, including the size and occurrence frequency. In this paper, a laser ultrasound and interferometer inspection system is used to inspect the voids in lead-free solder bumps in ball grid array (BGA) packages. This system uses a pulsed Nd:YAG laser to induce ultrasound in the chip packages in the thermoelastic regime; and laser interferometer is used to measure the transient out-of-plane displacement response of the package surface to the laser irradiation. The quality of solder bumps is evaluated by analyzing the transient responses. In this work, voids were intentionally created by adding the volatile flux during the assembly process. By controlling the volume of flux dip, three different levels of voiding were proposed: void-free, relatively low and relatively high. The presence of voids in the solder bumps was first verified using 2-D X-ray techniques. Meanwhile, the built-in image-processing software in X-ray tool measured the void fraction to quantify the level of voiding. Then the laser ultrasound inspection system was used to evaluate the voids in these samples. By comparing the vibration responses from voided samples and void-free samples, it was found that the laser ultrasound inspection system is capable to differentiate samples with relatively high voiding from void-free samples while the relatively low voiding was below the resolution of the inspection system. Lastly, a further comparison between the void-free and voided solder bumps was carried out by the destructive cross-section technique. The comparisons between these three solder bump evaluation methods will be presented in this paper.

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