Advanced chip to wafer bonding: A flip chip to wafer bonding technology for high volume 3DIC production providing lowest cost of ownership

2009 ◽  
Author(s):  
A. Sigl ◽  
S. Pargfrieder ◽  
C. Pichler ◽  
C. Scheiring ◽  
P. Kettner
Keyword(s):  
Wafer Bonding ◽  
Flip Chip ◽  
High Volume ◽  
Cost Of Ownership ◽  
Bonding Technology

Temporary and Permanent Adhesives for Thin Wafer Handling and Assembly

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 001009-001032
Author(s):  
Mark Oliver ◽  
Jong-Uk Kim ◽  
Michael Gallagher ◽  
Zidong Wang ◽  
Janet Okada ◽  
...  
Keyword(s):  
Wafer Bonding ◽  
Spin Coating ◽  
Bonding Temperature ◽  
High Volume ◽  
Wafer Surface ◽  
Process Time ◽  
Adhesion Promoter ◽  
Excellent Thermal Stability ◽  
Carrier Wafer ◽  
Bonding Technology

Temporary wafer bonding has emerged as the method of choice for handling silicon wafers during the thinning and high-temperature backside processing required for the manufacture of 3D device structures. Among the requirements for temporary wafer bonding materials to be used in high volume manufacturing are simple device and carrier wafer preparation, high-throughput wafer bonding, excellent thermal stability, and clean room-temperature release directly from the device wafer. We will present successful temporary wafer bonding using a new BCB (benzocyclobutene)-based material that can meet these requirements. For this temporary wafer bonding technology, wafer preparation involves spin coating the device wafer with the BCB-based adhesive to a thickness of up to 100 μm and spin coating the carrier wafer with an adhesion promoter. The wafers can then be bonded at temperatures as low as 80 °C for as short as 30 seconds. The low bonding temperature means the wafers can be loaded into a preheated wafer bonding tool, eliminating the time needed to heat and cool the bonding chucks during the bonding cycle. Also, no curing of the material is required during the bonding, enabling a short process time and high wafer throughput. Curing of the adhesive is done as a batch oven cure at 210 °C for one hour after which the material is stable enough for backside processes up to 300 °C. The material has been designed to adhere well to the carrier wafer and debond directly from the device wafer without any chemical or radiation pretreatment, leaving a clean device wafer surface in need of only mild cleaning before further processing.

High Precision Low Temperature Direct Wafer Bonding Technology for Wafer-Level 3D ICs Manufacturing

2016 ◽  
Vol 75 (9) ◽  
pp. 345-353 ◽  
Author(s):  
F. Kurz ◽  
T. Plach ◽  
J. Suss ◽  
T. Wagenleitner ◽  
D. Zinner ◽  
...  
Keyword(s):  
Low Temperature ◽  
High Precision ◽  
Wafer Bonding ◽  
Wafer Level ◽  
3D Ics ◽  
Direct Wafer Bonding ◽  
Bonding Technology

Smart‐Cut® : The Basic Fabrication Process for Unibond® Soi Wafers

1996 ◽  
Vol 446 ◽  
Author(s):  
A.J. Auberton‐Hervé ◽  
T. Barge ◽  
F. Metral ◽  
M. Bruel ◽  
B. Aspar ◽  
...  
Keyword(s):  
Wafer Bonding ◽  
Low Cost ◽  
Bulk Silicon ◽  
High Quality ◽  
Thin Film Thickness ◽  
Hydrogen Implantation ◽  
Electric Behavior ◽  
Bonding Technology ◽  
Good Uniformity ◽  
Quality Surface

AbstractThe advantage of SOI wafers for device manufacture has been widely studied. To be a real challenger to bulk silicon, SOI producers have to offer SOI wafers in large volume and at low cost. The new Smart‐Cut® SOI process used for the manufacture of the Unibond® SOI wafers answers most of the SOI wafer manufacturability issues. The use of Hydrogen implantation and wafer bonding technology is the best combination to get good uniformity and high quality for both the SOI and buried oxide layer. In this paper, the Smart‐Cut® process is described in detail and material characteristics of Unibond® wafers such as crystalline quality, surface roughness, thin film thickness homogeneity, and electric behavior.

Varifocal mirror integrated with scanner using wafer bonding technology

2016 ◽  
Author(s):  
Kenta Nakazawa ◽  
Takashi Sasaki ◽  
Hiromasa Furuta ◽  
Jiro Kamiya ◽  
Hideki Sasaki ◽  
...  
Keyword(s):  
Wafer Bonding ◽  
Bonding Technology

Low Temperature flip chip bonding technology applicable to flexible hybrid electronics in the IoT era

2019 ◽  
Vol 2019 (DPC) ◽  
pp. 000474-000518
Author(s):  
Hiroshi Komatsu
Keyword(s):  
Screen Printing ◽  
Flip Chip ◽  
Bonding Temperature ◽  
Complex Form ◽  
Fine Tuning ◽  
Electric Resistance ◽  
Flip Chip Bonding ◽  
Strong Adhesion ◽  
Bonding Technology ◽  
Ag Paste

Since its early days of the industry, electronics apparatus has been in a rigid and flat surfaced case. ICs have been soldered on rigid substrate at high bonding temperature. However, in the IoT era, electronics components connect with the variety of applications which require different forms and shapes of outlook which lead substrate and board should be flexible and complex form. Conventional flip chip bonding technology, such as solder bump and copper pillar, need to raise bonding temperature around 260-degree C, eventually does not satisfy this flexile hybrid electronics (FHE) application requirement. We have originally developed flip chip bonding technology which consists of the bump formation by Conductive Paste (CP) printing followed by Non-Conductive Paste (NCP) dispensing and flip chip bonding at temperature as low as 120-degree C. Bumps with silver particle loaded epoxy resin on substrate were formed by screen printing. This enable us to make fine bump formation down to 60um minimum bump pitch and 30um bump diameter with tuning of screen-printing process. After the bump formation, NCP dispensing and flip chip bonding at 120-degree C which secure reasonable low electric resistance, 8×1E-4 ohm cm2, and strong adhesion of chip and substrate. The bonding temperature of this technology can be lowered down to 80-degree C without much difficulties, but just by fine tuning of Ag paste and its contents. This momentum will create a lot more of future applications and be one of the core technologies in the coming IoT era in FHE.

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