Laser Lift-Off of the Sapphire Substrate for Fabricating Through-AlN-Via Wafer Bonded Absorption Layer Removed Thin Film Ultraviolet Flip Chip LED

In this study we report chip fabrication process that allows the laser lift-off of the sapphire substrate for the transfer of the GaN based thin film flip chip to the carrier wafer. The fabrication process includes 365-nm ultraviolet flip chip LED wafer align bonding with through-AlN-via wafer and sapphire laser lift-off. n-holes with the diameter of 100 µm were etched on the GaN epilayers for accessing n-type GaN. Through-AlN-via size was 110-µm and filled by Cu electroplating method for the electrical connection. Mechanical stabilization to prevent the GaN epilayers cracking and fragmentation during laser lift-off was achieved by utilizing epoxy based SU-8 photoresist support.

Design and performance evaluation of thin-film actuators based on flexible Ni-Co substrates

This paper proposes a new design of bimorph-type electrothermal actuators based on flexible Ni-Co substrates and describes the results of the finite element method (FEM) simulation and performance evaluation of the actuators. In the design of the actuators, a multilayer structure consisting of an adhesion layer, two insulation layers, and a Pt (platinum) heater layer was formed on the Ni-Co flexible substrate that was patterned in an individual shape. The thin-film actuators proposed in this study could be detached from a Si carrier wafer and adhered to other micro or macrostructural elements. To investigate the temperature distribution and mechanical behavior of the actuators, multiphysics FEM simulations combining electrothermal and static structural analyses were carried out. The actuators were fabricated using conventional microfabrication and electroplating technologies on Si carrier wafer; then, the actuators were peeled off from the carrier wafer using the release process proposed in this paper. After fabricating the actuators, the deflection of their tips was evaluated and compared with that obtained from the FEM simulations.

High Heat Resistant Peelable Temporary Bonding Film and New Debonding System with Xe Flash Light Irradiation

We have developed a new temporary bonding film (TBF) and new debonding system with Xe flash light irradiation, named photonic release system, for advanced package assembly process. Since new TBF has a high Tg over 200 °C after curing and shows good chemical resistance to developer, resist stripper, and plating chemicals, no delamination, voiding, and swelling were observed after thermal and chemical treatment in the bonded structure of wafer and glass carrier. In addition, by adopting a metal-sputtered glass carrier, wafer could be debonded by Xe flash light irradiation in less than 1 ms through the glass carrier with no damage. Residual TBF on the wafer surface could be peeled off smoothly at ambient temperature without residue on the wafer. In this research, we also demonstrated the good applicability of this temporary bonding film to the typical packaging process by using test vehicle including 12 inch mold wafer and the advantage of photonic release system.

Temporary and permanent bonding enables 3D integration of ultrathin wafers

Rising demand in memory is just one example how 3D integration is still gaining momentum. Not only the form factor but also performance is improved for several 3D integration applications by reducing the wafer thickness. Two competing process flows using thin wafers are to carry out for 3D integration today. Firstly, two wafers can be bonded face-to-face with subsequent thinning without the need to handle a thin wafer. However, some chip designs require a face-to-back stacking of thin wafers, where temporary bonding becomes an inevitable process step. In this case, the challenge of the temporary bonding process is different to traditional stacking on chip level, where usually the wafers are diced after debonding and then stacked on chip level, which means die thicknesses are typically in the range of 50 μm. The goal of wafer level transfer is a massive reduction of the wafer thickness. Therefore temporary and permanent bonding has to be combined to enable stacking on wafer level with very thin wafers. The first step is temporary bonding of the device wafer with the temporary carrier through an adhesive interlayer, followed by thinning and other backside processes. Afterwards the thinned wafer is permanently bonded to the target wafer before debonding from the carrier wafer. This can be repeated several times to be suitable for example a high bandwidth memory, where several layers of DRAM are stacked on top of each other. Another application is the memory integration on processors, or die segmentation processes. The temporary bonding process flow has to be very well controlled in terms of total thickness variations (TTV) of the intermediate adhesive between device and carrier wafer. The requirements for the temporary bonding adhesive include offering sufficient adhesion between device and carrier wafer for the subsequent processes. The choice of the material class for this study is the Brewer Science dual layer material comprising of a curable layer which offers high mechanical stability to enable low TTV during the thinning process and a release layer for mechanical debond process. The release layer must lead to a successful debond but prevent spontaneous debonding during grinding and other processes. Total thickness variation values of the adhesive will be analyzed in dependence of the adhesive layer thickness as this is a key criterion for a successful implementation at the manufactures. Besides the TTV the mechanical stability during grinding will be evaluated by CSAM to make sure no delamination has happened. For feasibility of the total process flow it is important that the mechanical debonding requires less force compared to the separation of the permanent bonded wafers. Other process parameters such as edge trimming of the device wafer as well as edge removal of the mechanical debond release layer are investigated.

Sacrificial Layer Technique for Releasing Metallized Multilayer SU-8 Devices

The low fabrication cost of SU-8-based devices has opened the fields of point-of-care devices (POC), µTAS and Lab-on-Chip technologies, which call for cheap and disposable devices. Often this translates to free-standing, suspended devices and a reusable carrier wafer. This necessitates a sacrificial layer to release the devices from the substrates. Both inorganic (metals and oxides) and organic materials (polymers) have been used as sacrificial materials, but they fall short for fabrication and releasing multilayer SU-8 devices. We propose photoresist AZ 15nXT (MicroChemicals GmbH, Ulm, Germany) to be used as a sacrificial layer. AZ 15nXT is stable during SU-8 processing, making it suitable for fabricating free-standing multilayer devices. We show two methods for cross-linking AZ 15nXT for stable sacrificial layers and three routes for sacrificial release of the multilayer SU-8 devices. We demonstrate the capability of our release processes by fabrication of a three-layer free-standing microfluidic electrospray ionization (ESI) chip and a free-standing multilayer device with electrodes in a microchannel.

Critical Process Parameters And Failure Analysis For Temporary Bonded Wafer Stacks

Temporary bonding is a ley process for almost any 3D integration scheme. It offers not only more stability during the thinning process but also allows handling for backside processing of thin wafers like interposers during subsequent process steps [1–2]. Although the temporary bonding technology is already used in high volume manufacturing and has proven high yield process, nevertheless, some limitation appears for some specific applications [3-4-5]. One critical failure origin is delamination, which can lead to wafer breakage and therefore yield loss. This separation of the device wafer and the carrier wafer typically occurs when the temporary bonded wafer stack (device wafer, carrier wafer and temporary bonding adhesive in between) experiences further processing done under high temperature and low vacuum like PECVD deposition. Further insight into processing parameters and a better understanding of the key contributing factors as well as its dependencies help to prevent this failure. To investigate the root cause of the delamination, thermoplastic materials, which are widely used for temporary bonding and debonding applications have been used as temporary bonding adhesives in this work. Different process parameters were investigated individually but also in combination to find the origin of the delamination. These parameters include post thinning annealing temperature, which was varied up to 370C, vacuum level, thermal gradient, bow and warp and intrinsic stress of the thin device wafer. After evaluation of the main parameters affecting the delamination appearance, two extreme cases were experimented in order to check the hypothesis. The first one exhibits delaminations even using a very soft processing conditions for a temporary bonding integration and the second case is able to withstand extreme processing conditions like high temperature up to 370C under vacuum of about 1mbar without delamination appearance. In addition, during this work, the mechanical coupling existing between the carrier and the device wafer thanks to the adhesive has been investigated. Here, a thermoplastic material was used in a temporary bonded structures using wafers with different coefficients of thermal expansion (CTE). During thermal treatment, this CTE difference induce important internal stress bow of the wafer stack. The temperature dependence of the mechanical coupling is monitored during the annealing. A mechanical decoupling between the two wafers occurs when above the polymer glass transition temperature. As a result, the rheology of the thermoplastic layer is found as a contributor to the delamination mechanism. Critical combinations of process parameters in temporary bonding process are then clearly identified and will be presented in this work.

Technologies for Wafer Level MEMS Capping based on Permanent and Temporary Wafer Bonding

Further cost reduction and miniaturization of electronic systems requires new concepts for highly efficient packaging of MEMS components like RF resonators or switches, quartz crystals, bolometers, BAWs etc. This paper describes suitable base technologies for the miniaturized, low-cost wafer level chip-scale packaging of such MEMS. The approaches are based on temporary handling and permanent bonding of cap structures using adhesives or solder onto passive or active silicon wafers which are populated with MEMS components or the MEMS wafer themselves. Firstly, an overview of the possible packaging configurations based on different types of MEMS is discussed where TSV based and non-TSV based packaging solutions are distinguished in general. The cap structure for the TSV based solution can have the same size as the MEMS carrying substrate, since the electrical contacts for the MEMS can be routed either thought the cap or base substrate. Thus, full format cap wafers can be used in a regular wafer to wafer bonding process to create the wafer level cavity packages. However, if no TSVs are present in the cap or base substrate, the cap structure needs to be smaller than the base chip, so that electrical contacts outside the cap area can be accessed after the caps were bonded. Such a wafer level capping with caps smaller than the corresponding base chips can be obtained in two ways. The first approach is based on fabrication and singulation of the caps followed by their temporary face up assembly in the desired pattern on a help wafer. In a subsequent wafer to wafer bonding sequence all caps are transferred onto the base wafer. Finally the help wafer is removed from the back side of the bonded caps. This approach of reconfigured wafer bonding is especially used for uniform cap patterns or, if MEMS have an own bond frame structure. In that case no additional cap is required, since the MEMS can act as their own cap. The second approach is based on cap structure fabrication using a compound wafer stack consisting of two temporary bonded wafers. One wafer acts as carrier wafer whereas the other wafer is processed to form cap structures. Processes like thinning, silicon dry etching, deposition and structuring of polymer or metal bonding frames are performed to generate free-standing and face-up directed cap structures. The so created “cap donor wafer” is used in a wafer to wafer bonding process to bond all caps permanently to the corresponding MEMS base wafer. Finally, the temporary bonded carrier wafer is removed from the backside of the transferred caps. With that approach a fully custom specific and selective wafer level capping is possible featuring irregular cap patterns and locations on the MEMS base wafer. Examples like the selective capping process for RF MEMS switches are presented and discussed in detail. All processes were performed at 200mm wafer level.