Temporary and Permanent Adhesives for Thin Wafer Handling and Assembly

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 001009-001032
Author(s):  
Mark Oliver ◽  
Jong-Uk Kim ◽  
Michael Gallagher ◽  
Zidong Wang ◽  
Janet Okada ◽  
...  

Temporary wafer bonding has emerged as the method of choice for handling silicon wafers during the thinning and high-temperature backside processing required for the manufacture of 3D device structures. Among the requirements for temporary wafer bonding materials to be used in high volume manufacturing are simple device and carrier wafer preparation, high-throughput wafer bonding, excellent thermal stability, and clean room-temperature release directly from the device wafer. We will present successful temporary wafer bonding using a new BCB (benzocyclobutene)-based material that can meet these requirements. For this temporary wafer bonding technology, wafer preparation involves spin coating the device wafer with the BCB-based adhesive to a thickness of up to 100 μm and spin coating the carrier wafer with an adhesion promoter. The wafers can then be bonded at temperatures as low as 80 °C for as short as 30 seconds. The low bonding temperature means the wafers can be loaded into a preheated wafer bonding tool, eliminating the time needed to heat and cool the bonding chucks during the bonding cycle. Also, no curing of the material is required during the bonding, enabling a short process time and high wafer throughput. Curing of the adhesive is done as a batch oven cure at 210 °C for one hour after which the material is stable enough for backside processes up to 300 °C. The material has been designed to adhere well to the carrier wafer and debond directly from the device wafer without any chemical or radiation pretreatment, leaving a clean device wafer surface in need of only mild cleaning before further processing.

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 000419-000441 ◽  
Author(s):  
David Fleming ◽  
Jong-Uk Kim ◽  
Janet Okada ◽  
Kevin Wang ◽  
Michael Gallagher ◽  
...  

The development of adhesives that enable handling, processing, and assembly of thin wafers and die is a key technical challenge for the realization of 3D devices. We will present on temporary adhesive technology for processing of thinned wafers that is amenable to either mechanical or laser-assisted debonding that can occur at room temperature. Temporary wafer bonding has emerged as the method of choice for handling silicon wafers during the thinning and high-temperature backside processing required for the manufacture of 3D device structures. Among the requirements for temporary wafer bonding materials to be used in high volume manufacturing are simple device and carrier wafer preparation, high-throughput wafer bonding, thermal stability to 300 °C or higher, and clean room-temperature release directly from the device wafer using either mechanical or laser-assisted debonding We will present successful temporary wafer bonding using a BCB (benzocyclobutene)-based material that can meet these requirements. The mode of adhesive release from a device wafer will be discussed in detail as it relates to wafer thinning and handling, and material physical properties and resistances will be expressed. Formulation requirements needed for successful debonding will be presented, with an emphasis on a laser-debonding scheme that utilizes either a 248nm or 308nm laser source capable of ablating a laser sensitive layer residing between a glass carrier and the temporary wafer bonding material. Successful room temperature tape-peeling of the adhesive film after ablation and carrier removal will be discussed.


2016 ◽  
Vol 75 (9) ◽  
pp. 345-353 ◽  
Author(s):  
F. Kurz ◽  
T. Plach ◽  
J. Suss ◽  
T. Wagenleitner ◽  
D. Zinner ◽  
...  

1986 ◽  
Vol 67 ◽  
Author(s):  
Chris R. Ito ◽  
M. Feng ◽  
V. K. Eu ◽  
H. B. Kim

ABSTRACTA high-volume epitaxial reactor has been used to investigate the feasibility for the production growth of GaAs on silicon substrates. The reactor is a customized system which has a maximum capacity of 39 three-inch diameter wafers and can accommodate substrates as large as eight inches in diameter. The MOCVD material growth technique was used to grow GaAs directly on p-type, (100) silicon substrates, three and five inches in diameter. The GaAs surfaces were textured with antiphase boundaries. Double-cyrstal rocking curve measurements showed single-cyrstal GaAs with an average FWHMof 520 arc seconds measured at four points over the wafer surface. Within-wafer thickness uniformity was ± 4% with a wafer-to-wafer uniformity of ± 2%. Photoluminescence spectra showed Tour peaks at 1.500, 1.483, 1.464, and 1.440 ev. Schottky diodes were fabricated on the GaAs on silicon material.


1996 ◽  
Vol 446 ◽  
Author(s):  
A.J. Auberton‐Hervé ◽  
T. Barge ◽  
F. Metral ◽  
M. Bruel ◽  
B. Aspar ◽  
...  

AbstractThe advantage of SOI wafers for device manufacture has been widely studied. To be a real challenger to bulk silicon, SOI producers have to offer SOI wafers in large volume and at low cost. The new Smart‐Cut® SOI process used for the manufacture of the Unibond® SOI wafers answers most of the SOI wafer manufacturability issues. The use of Hydrogen implantation and wafer bonding technology is the best combination to get good uniformity and high quality for both the SOI and buried oxide layer. In this paper, the Smart‐Cut® process is described in detail and material characteristics of Unibond® wafers such as crystalline quality, surface roughness, thin film thickness homogeneity, and electric behavior.


2020 ◽  
Vol 2020 (1) ◽  
pp. 000302-000306
Author(s):  
Yuta Akasu ◽  
Emi Miyazawa ◽  
Tetsuya Enomoto ◽  
Yasuyuki Oyama ◽  
Shogo Sobue ◽  
...  

Abstract We have developed a new temporary bonding film (TBF) and new debonding system with Xe flash light irradiation, named photonic release system, for advanced package assembly process. Since new TBF has a high Tg over 200 °C after curing and shows good chemical resistance to developer, resist stripper, and plating chemicals, no delamination, voiding, and swelling were observed after thermal and chemical treatment in the bonded structure of wafer and glass carrier. In addition, by adopting a metal-sputtered glass carrier, wafer could be debonded by Xe flash light irradiation in less than 1 ms through the glass carrier with no damage. Residual TBF on the wafer surface could be peeled off smoothly at ambient temperature without residue on the wafer. In this research, we also demonstrated the good applicability of this temporary bonding film to the typical packaging process by using test vehicle including 12 inch mold wafer and the advantage of photonic release system.


Author(s):  
J. Wei ◽  
S. S. Deng ◽  
C. M. Tan

Silicon-to-silicon wafer bonding by sol-gel intermediate layer has been performed using acid-catalyzed tetraethylthosilicate-ethanol-water sol solution. High bond strength near to the fracture strength of bulk silicon is obtained at low temperature, for example 100°C. However, The bond efficiency and bond strength of this intermediate layer bonding sharply decrease when the bonding temperature increases to elevated temperature, such as 300 °C. The degradation of bond quality is found to be related to the decomposition of residual organic species at elevated bonding temperature. The bubble generation and the mechanism of the high bond strength at low temperature are exploited.


Author(s):  
Kenta Nakazawa ◽  
Takashi Sasaki ◽  
Hiromasa Furuta ◽  
Jiro Kamiya ◽  
Hideki Sasaki ◽  
...  

Author(s):  
Hiroshi Komatsu

Since its early days of the industry, electronics apparatus has been in a rigid and flat surfaced case. ICs have been soldered on rigid substrate at high bonding temperature. However, in the IoT era, electronics components connect with the variety of applications which require different forms and shapes of outlook which lead substrate and board should be flexible and complex form. Conventional flip chip bonding technology, such as solder bump and copper pillar, need to raise bonding temperature around 260-degree C, eventually does not satisfy this flexile hybrid electronics (FHE) application requirement. We have originally developed flip chip bonding technology which consists of the bump formation by Conductive Paste (CP) printing followed by Non-Conductive Paste (NCP) dispensing and flip chip bonding at temperature as low as 120-degree C. Bumps with silver particle loaded epoxy resin on substrate were formed by screen printing. This enable us to make fine bump formation down to 60um minimum bump pitch and 30um bump diameter with tuning of screen-printing process. After the bump formation, NCP dispensing and flip chip bonding at 120-degree C which secure reasonable low electric resistance, 8×1E-4 ohm cm2, and strong adhesion of chip and substrate. The bonding temperature of this technology can be lowered down to 80-degree C without much difficulties, but just by fine tuning of Ag paste and its contents. This momentum will create a lot more of future applications and be one of the core technologies in the coming IoT era in FHE.


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